Secure processing unit systems and methods

• US 7,430,585 B2
• Filed: 09/27/2006
• Issued: 09/30/2008
• Est. Priority Date: 08/20/1999
• Status: Expired due to Fees

• Current Assignee: Intertrust Technologies Corporation (Fidelio Acquisition Co LLC)
• Original Assignee: Intertrust Technologies Corporation (Fidelio Acquisition Co LLC)
• Inventors: Sibert, W. Olin
• Primary Examiner(s): Flynn; Nathan
• Assistant Examiner(s): Shin; Kyung H
• Application Number:
  US11/528,752
• Publication Number:
  US 20070124409A1
• Time in Patent Office: 734 Days
• Field of Search: 709/216, 713/164, 713/189, 713/193, 713/194, 380/225, 380/221, 711/103, 711/206, 711/152, 711/153
• US Class Current: 709/216
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 21/6218 to a system of files or objects, e.g. local or distributed file system or database
• CPC Class Codes: G06F 21/6227 where protection concerns the structure of data, e.g. records, types, queries
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06Q 50/188 Electronic negotiation
• CPC Class Codes: H04L 63/0823 using certificates cryptographic mechanisms or cryptographic arrangements for entity authentication involving certificates H04L9/3263
• CPC Class Codes: H04L 63/126 the source of the received data

Abstract

A hardware Secure Processing Unit (SPU) is described that can perform both security functions and other information appliance functions using the same set of hardware resources. Because the additional hardware required to support security functions is a relatively small fraction of the overall device hardware, this type of SPU can be competitive with ordinary non-secure CPUs or microcontrollers that perform the same functions. A set of minimal initialization and management hardware and software is added to, e.g., a standard CPU/microcontroller. The additional hardware and/or software creates an SPU environment and performs the functions needed to virtualize the SPU'"'"'s hardware resources so that they can be shared between security functions and other functions performed by the same CPU.

Claims

1. In a secure processing unit comprising a memory management unit, an internal memory unit, and processor security registers, a method of restricting access to memory, the method comprising:

using one or more level-one page table entries of a plurality of page table entries in a level-one page table to indicate whether entries in a level-two page table corresponding with the one or more level-one page table entries may designate certain predefined memory regions based on one or more predefined attributes respectively contained in the one or more level-one page table entries; and

restricting access by certain software components or processor modes to predefined memory regions based on access control data, wherein the access control data are stored in a critical address register, the critical address register comprising one of the processor security registers.

2. The method of claim 1, wherein the internal memory unit includes secure random access memory, secure non-volatile memory, and secure read-only memory.

3. The method of claim 2, wherein the secure non-volatile memory contains a cryptographic key.

4. The method of claim 2, wherein the secure non-volatile memory is powered by a battery.

5. The method of claim 4, wherein the secure non-volatile memory contains a cryptographic key.

6. The method of claim 1, wherein the internal memory unit includes a unique identifier for the secure processing unit, a private cryptographic key, and a public cryptographic key.

7. The method of claim 6, wherein the internal memory unit further includes a cryptographic certificate linking the unique identifier and the public cryptographic key.

8. The method of claim 1, wherein one or more level-two page tables are configured so as to be unable to designate the predefined memory regions are stored in memory locations other than the internal memory unit.

9. In an information appliance comprising a secure processing unit, the secure processing unit comprising a memory management unit, an internal memory unit, and processor security registers, a method comprising:

indicating, using one or more level-one page table entries of a plurality of page table entries in a level-one page table, whether entries in a level-two page table corresponding with the one or more level-one page table entries may designate certain predefined memory regions based on one or more predefined attributes respectively contained in the one or more level-one page table entries;

restricting access by certain software components or processor modes to predefined memory regions based on access control data, wherein the access control data are stored in a critical address register, the critical address register comprising one of the processor security registers; and

enabling performance, by the secure processing unit, of both secure processing operations and at least some processing operations performed by a conventional information appliance processing unit.

10. The method of claim 9, wherein the information appliance is an appliance selected from:

a television set-top box, a portable audio player, a portable video player, a cellular telephone, a personal computer, and a workstation.

11. The method of claim 9, wherein the secure processing unit is the information appliance'"'"'s primary processing unit.

12. The method of claim 9, wherein the secure processing unit is the information appliance'"'"'s only processing unit.

13. The method of claim 9, wherein the level-one page table and the level-two page tables that may designate the predefined memory regions are stored in the internal memory unit.

14. The method of claim 9, wherein the internal memory unit includes secure random access memory, secure non-volatile memory, and secure read-only memory.

15. The method of claim 14, wherein the secure non-volatile memory contains a cryptographic key.

16. The method of claim 14, wherein the secure non-volatile memory is powered by a battery.

17. The method of claim 16, wherein the secure non-volatile memory contains a cryptographic key.

18. The method of claim 9, wherein the internal memory unit includes a unique identifier for the secure processing unit, a private cryptographic key, and a public cryptographic key.

19. The method of claim 18, wherein the internal memory unit further includes a cryptographic certificate linking the unique identifier and the public cryptographic key.

20. The method of claim 9, wherein one or more level-two page tables are configured so as to be unable to designate the predefined memory regions are stored in memory locations other than the internal memory unit.