Data transfer control device and electronic equipment

• US 7,430,618 B2
• Filed: 12/22/2004
• Issued: 09/30/2008
• Est. Priority Date: 07/15/1999
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Ishida, Takuya, Kamihara, Yoshiyuki
• Primary Examiner(s): Dang; Khanh
• Assistant Examiner(s): Cleary; Thomas J
• Application Number:
  US11/017,858
• Publication Number:
  US 20050105549A1
• Time in Patent Office: 1,378 Days
• Field of Search: 710/5, 710/29, 710/33, 710/52, 710/57, 710105-107, 709231-232, 370/218, 370/389, 370/392, 370/902, 370/912
• US Class Current: 710/5
• CPC Class Codes: H04L 12/2801 Broadband local area networks
• CPC Class Codes: H04L 12/40052 High-speed IEEE 1394 serial bus bus transfer protocol on a daisy chain bus using an embedded synchronisation G06F13/426
• CPC Class Codes: H04L 12/40071 Packet processing; Packet format adaptation of digital video signals for transport over a specific network H04N21/2381, H04N21/4363, H04N21/4381; packet switches H04L49/00; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9042 Separate storage for different parts of the packet, e.g. header and payload
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]

Abstract

An objective of the present invention is to provide a data transfer control device and electronic equipment which make it possible to reduce processing overheads in the firmware and implement high-speed data transfer. In a data transfer control device in accordance with the IEEE 1394 standard, the header of a packet is written to a header area, the ORB (data for SBP-2) of the packet is written to an ORB area, and the stream (data for the application layer) of the packet is written to a stream area. The stream area is managed by hardware in accordance with full and empty signals. Indication information is comprised within a transaction label tl of a request packet, and the header, ORB, and stream of a response packet are written to areas indicated by the indication information comprised within tl, when the response packet is received. The device is also provided with registers TSR and TER that contain addresses TS and TE for securing a transmission area in the stream area and registers RSR and RER that contain addresses RS and RE for securing a reception area therein.

Claims

1. A data transfer control device for transferring data between a plurality of nodes connected to a bus, the data transfer control device comprising:

a link circuit that provides services for packet transfer between the plurality of nodes;

a write circuit that writes a packet that has been received through the link circuit to a packet storage memory; and

a packet division circuit that writes control information of the packet to a control information area of the packet storage memory, writes first data of the packet for a first layer to a first data area of the packet storage memory, and writes second data of the packet for a second layer that is a layer above the first layer to a second data area of the packet storage memory,

the first data being command data used by a protocol of the first layer and the second data being stream data used by an application layer, and the second data being read sequentially from the second data area and the read second data is transferred to an application layer device,

the data transfer control device transmitting a request packet for starting a transaction to a responding node among the plurality of nodes,

the request packet including transaction identification information that contains indication information, the indication information indicating a process to be performed when the data transfer control device receives a response packet as the packet from the responding node, the transaction identification information being a transaction label, and

the first data and the second data of the response packet being written into separate data areas as specified by the indication information within the transaction identification information of the response packet, when the response packet from the responding node is received.

2. The data transfer control device as defined in claim 1, further comprising an area management circuit that makes a full signal go active when the second data area is full, to inhibit the write circuit from writing the second data to the second data area, and makes an empty signal go active when the second data area is empty, to inhibit the second layer from reading the second data from the second data area.

3. The data transfer control device as defined in claim 1, data transfer being in accordance with the IEEE 1394 standard.

4. The data transfer control device as defined in claim 1,

the link circuit comprising a tag generation circuit that generates a tag being information for delimiting areas, and

the packet division circuit writing control information of the packet to the control information area, writing the first data of the packet for the first layer to the first data area, and writing the second data of the packet for the second layer to the second data area, based on the tag generated by the tag generation circuit.

5. The data transfer control device as defined in claim 1, the first data area being an operational request block area and the second area being a stream area.

6. Electronic equipment comprising:

a data transfer control device for transferring data between a plurality of nodes connected to a bus, comprising;

a link circuit that provides services for packet transfer between the plurality of nodes;

a write circuit that writes a packet that has been received through the link circuit to a packet storage memory; and

a packet division circuit that writes control information of the packet to a control information area of the packet storage memory, writes first data of the packet for a first layer to a first data area of the packet storage memory, and writes second data of the packet for a second layer that is a layer above the first layer to a second data area of the packet storage memory,

the first data being command data used by a protocol of the first layer and the second data being stream data used by an application layer, and the second data being read sequentially from the second data area and the read second data is transferred to an application layer device,

the data transfer control device transmitting a request packet for starting a transaction to a responding node among the plurality of nodes,

the request packet including transaction identification information that contains indication information, the indication information indicating a process to be performed when the data transfer control device receives a response packet as the packet from the responding node, the transaction identification information being a transaction label, and

the first data and the second data of the response packet being written into separate data areas as specified by the indication information within the transaction identification information of the response packet, when the response packet from the responding node is received;

a device which performs given processing on data that has been received from another node through the data transfer control device and a bus; and

a device which outputs or stores data that has been subjected to processing.

7. Electronic equipment comprising:

a data transfer control device for transferring data between a plurality of nodes connected to a bus, comprising;

a link circuit that provides services for packet transfer between the plurality of nodes;

a write circuit that writes a packet that has been received through the link circuit to a packet storage memory; and

a packet division circuit that writes control information of the packet to a control information area of the packet storage memory, writes first data of the packet for a first layer to a first data area of the packet storage memory, and writes second data of the packet for a second layer that is a layer above the first layer to a second data area of the packet storage memory,

the first data being command data used by a protocol of the first layer and the second data being stream data used by an application layer, and the second data being read sequentially from the second data area and the read second data is transferred to an application layer device,

the data transfer control device transmitting a request packet for starting a transaction to a responding node among the plurality of nodes,

the request packet including transaction identification information that contains indication information, the indication information indicating a process to be performed when the data transfer control device receives a response packet as the packet from the responding node, the transaction identification information being a transaction label, and

the first data and the second data of the response packet being written into separate data areas as specified by the indication information within the transaction identification information of the response packet, when the response packet from the responding node is received;

a device which performs given processing on data that is to be transferred to another node through the data transfer control device and a bus; and

a device which takes in data to be subjected to processing.

8. A data transfer control device for transferring data between a plurality of nodes connected to a bus, the data transfer control device comprising:

a link circuit that provides services for packet transfer between the plurality of nodes;

a write circuit that writes a packet that has been received through the link circuit to a packet storage memory; and

a packet division circuit that writes control information of the packet to a control information area of the packet storage memory, writes first data of the packet for a first layer to a first data area of the packet storage memory, and writes second data of the packet for a second layer that is a layer above the first layer to a second data area of the packet storage memory;

a first bus for connecting to an application layer device;

a second bus for transferring control signals of the data transfer control device from a control device;

a third bus for connecting to a physical layer device;

a fourth bus for connecting to the packet storage memory;

a fifth bus for connecting to a circuit that implements part of the first layer protocol by hardware; and

an arbitration circuit that performs the arbitration for establishing a data path between one of the first, second, third, and fifth buses and the bus,

the first data being command data used by a protocol of the first layer and the second data being stream data used by an application layer, and the second data being read sequentially from the second data area and the read second data is transferred to the application layer device.