Semiconductor device and method of manufacturing the same

• US 7,432,135 B2
• Filed: 08/09/2006
• Issued: 10/07/2008
• Est. Priority Date: 11/14/2005
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Takahashi, Hideki
• Primary Examiner(s): Lee; Calvin
• Application Number:
  US11/463,502
• Publication Number:
  US 20070108468A1
• Time in Patent Office: 790 Days
• Field of Search: 438135-140, 438/268, 257133-139
• US Class Current: 438/140
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device, including: a semiconductor substrate of a first conductivity type having a first and second major surfaces; a first conductivity type semiconductor layer formed on the first major surface of the semiconductor substrate; a base layer of a second conductivity type formed on the first major surface of the semiconductor layer and separated by the semiconductor layer from the semiconductor substrate; a pair of groove portions penetrating the base layer from the first major surface and reaching at least the semiconductor layer; an insulation film disposed inside the groove portion and a gate electrode formed inside the groove portion through the insulation film; a first conductivity type semiconductor layer and a second conductivity type semiconductor layer formed on the second major surface of the semiconductor substrate; and an emitter region disposed on the first major surface of the base layer and along the groove portions, wherein a transistor controlling a current flowing in the base layer by the gate electrode and a diode made of the semiconductor layer and the base layer are disposed within the semiconductor device, and the emitter region is disposed only in an area which is between the pair of groove portions.

Claims

1. A method of manufacturing a semiconductor device having a transistor controlling a current flowing in a base layer by a gate electrode and a diode, comprising the steps of:

preparing a semiconductor substrate of a first conductivity type having first and second major surfaces;

forming a first conductivity type semiconductor layer on the first major surface of the semiconductor substrate;

forming a base layer of a second conductivity type on the surface of the semiconductor layer;

forming a pair of groove portions penetrating the base layer from the first major surface and reaching at least the semiconductor layer;

disposing an insulation film inside the groove portion and forming a gate electrode inside the groove portion through the insulation film forming an inter-layer insulation film to cover the top of the groove portion;

forming a first conductivity type semiconductor layer and a second conductivity type semiconductor layer on the second major surface of the semiconductor substrate; and

disposing an emitter region along the groove portions only in a section of the base layer on the first major surface and located between the pair of groove portions.

2. The manufacturing method according to claim 1, comprising a step of forming at least two groove sets each formed by the pair of groove portions and further forming a second groove portion between the groove sets which are adjacent to each other.

3. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type having a first and second major surfaces;

a first conductivity type semiconductor layer formed on the first major surface of the semiconductor substrate;

a base layer of a second conductivity type formed on the first major surface of the semiconductor layer and separated by the semiconductor layer from the semiconductor substrate;

a pair of groove portions penetrating the base layer from the first major surface and reaching at least the semiconductor layer;

an insulation film disposed inside the groove portion and a gate electrode formed inside the groove portion through the insulation film an inter-layer insulation film formed to cover the top of the groove portion;

a first conductivity type semiconductor layer and a second conductivity type semiconductor layer formed on the second major surface of the semiconductor substrate; and

an emitter region disposed on the first major surface of the base layer and along the groove portions,

wherein a transistor controlling a current flowing in the base layer by the gate electrode and a diode made of the semiconductor layer and the base layer are disposed within the semiconductor device, and

the emitter region is disposed only in an area which is between the pair of groove portions.

4. The semiconductor device according to claim 3, wherein there are at least two groove sets each formed by the pair of groove portions, and the gap between the pair of groove portions is narrower than the gap between the groove sets.

5. The semiconductor device according to claim 3, wherein there are at least two groove sets each formed by the pair of groove portions, and a second groove portion seating a conductive layer through the insulation film is provided between the groove sets which are adjacent to each other.

6. The semiconductor device according to claim 5, wherein the gap between the pair of groove portions is approximately equal to the gaps between the groove portion and the second groove portion.

7. The semiconductor device according to claim 5, wherein there are plurality of the second groove portions provided between the groove sets which are adjacent to each other.

8. The semiconductor device according to claim 7, wherein the gap between the second groove portions which are adjacent to each other is narrower than the gap between the pair of groove portions.

9. The semiconductor device according to claim 5, wherein the second groove portion is provided in the form of a lattice.

10. The semiconductor device according to claim 5, wherein the depth of the groove portion and the depth of the second groove portion are approximately the same.

11. The semiconductor device according to claim 5, wherein an emitter electrode is disposed on the first major surface of the semiconductor substrate, and the conductive layer inside the second groove portion is electrically connected with the emitter electrode.

12. The semiconductor device according to claim 3, wherein the plurality of the groove portions are shaped like stripes which are approximately parallel to each other, and the emitter region appears every other areas which are located between the groove portions.

13. The semiconductor device according to claim 3, wherein the groove portions are surrounded by the base layer which do not include the emitter region.

14. The semiconductor device according to claim 3, wherein the semiconductor layer comprises a low-lifetime area.