Body biasing structure of SOI

• US 7,432,552 B2
• Filed: 06/12/2006
• Issued: 10/07/2008
• Est. Priority Date: 06/11/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd., Seoul National University Industry Foundation (Seoul National University)
• Original Assignee: Samsung Electronics Co. Ltd., Seoul National University Industry Foundation (Seoul National University)
• Inventors: Park, Byung-Gook, Kim, Tae-Hoon, Park, II-Han
• Primary Examiner(s): Elms; Richard T.
• Assistant Examiner(s): Bernstein; Allison P
• Application Number:
  US11/423,696
• Publication Number:
  US 20060278927A1
• Time in Patent Office: 848 Days
• Field of Search: 257/347, 257/348, 257/349
• US Class Current: 257/349
• CPC Class Codes: H01L 29/78615 with a body contact

Abstract

A body biasing structure of devices connected in series on an SOI substrate is provided. According to some embodiments, the shallow junction of common source/drain regions enables all devices to bias by only one body contact on an SOI substrate like a conventional bulk MOSFET, and the floating body effect on an SOI substrate can be prevented.

Claims

1. A body biasing structure for Silicon-On-Insulator (SOI) devices comprising:

an SOI substrate;

an active region in the SOI substrate comprising;

a body biasing contact region;

a common active region connected to the body biasing contact region; and

a device active region connected to the common active region;

a first conducting layer, which is formed on an insulating layer over both one part of the body biasing contact region and one part of the common active region;

a second conducting layer, which is formed on an insulating layer over the device active region;

a source region, which is formed in the other part of the common active region, over which the first conducting layer is not formed;

a common source/drain region, which is formed in the device active region between the first conducting layer and the second conducting layer; and

a body region, which is formed in the active region, where the source region and the common source/drain region are not formed,

wherein the common source/drain region has a shallow junction to enable the second conducting layer to body bias through a body contact, which is formed on the body biasing contact region.

2. The structure of claim 1, wherein the device active region is two or more rectilinear regions connected vertically to the common active region with a predetermined width.

3. The structure of claim 2 further including:

a plurality of second conducting layers, which are each formed on an insulating layer over the device active region; and

a plurality of common source/drain regions, which are formed in the device active region between the plurality of second conducting layers.

4. The structure of claim 2, wherein the two or more rectilinear regions are spaced apart by a predetermined interval.

5. The structure of claim 3, wherein the plurality of common source/drain regions have a shallow junction to enable the plurality of second conducting layers to body bias through the body contact, which is formed on the body biasing contact region.

6. The structure of claim 1 further including:

a plurality of second conducting layers, which are each formed on an insulating layer over the device active region; and

a plurality of common source/drain regions, which are formed in the device active region between the plurality of second conducting layers.

7. The structure of claim 6, wherein the plurality of common source/drain regions have a shallow junction to enable the plurality of second conducting layers to body bias through the body contact, which is formed on the body biasing contact region.

8. The structure of claim 1, wherein the first conducting layer is a common gate line and the second conducting layer is a word line.

9. A body biasing structure for Silicon-On-Insulator (SOI) devices comprising:

an SOI substrate;

an active region in the SOI substrate comprising;

a body biasing contact region;

a common active region connected to the body biasing contact region; and

a device active region connected to the common active region;

a first conducting layer, which is formed on an insulating layer over both one part of the body biasing contact region and one part of the common active region;

a second conducting layer, which is formed on an insulating layer over the device active region;

a source region, which is formed in the other part of the common active region, over which the first conducting layer is not formed;

a common source/drain region, which is formed between the first conducting layer and the second conducting layer; and

a body region, which is formed in the active region, where the source region and the common source/drain region are not formed,

wherein SOI substrate comprises a buried oxide (BOX) layer, wherein the body region contacts the BOX layer and the insulating layers on which the first and second conducting layers are formed, and

wherein the body region extends below the first conducting layer, the second conducting layer and the common source/drain region contiguously from body biasing contact region to a location vertically below the second conducting layer.