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Endpoint event processing system

  • US 7,432,824 B2
  • Filed: 09/26/2006
  • Issued: 10/07/2008
  • Est. Priority Date: 07/24/2003
  • Status: Expired due to Term
First Claim
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1. An endpoint processor unit, comprising:

  • a processor block;

    a timer block that is arranged to provide at least one time based signal to the processor block;

    a memory block that is arranged to cooperate with the processor block;

    a conditioning block that is arranged to provide input level control and signal filtering using an input level control block connected to an anti-aliasing filter block, the input level control block being arranged to receive a line voltage input from a power distribution line and the anti-aliasing filter block configured to output an attenuated line voltage signal, wherein the line voltage input being transformed prior to being input to the conditioning block, andthe anti-aliasing filtering block providing a band-pass filter, wherein a center frequency of the band-pass filter being centered on a modulation frequency; and

    a processing block that is arranged to extract a digital bit stream from the line voltage input, the processing block comprising;

    a first signal processing block being arranged to provide an under-sampled digital signal from an analog input, wherein the first signal processing block comprises an analog-to-digital converter, wherein the analog-to-digital converter being arranged to provide an interface between the attenuated line voltage signal and a second signal processing block, wherein the attenuated line voltage signal includes encoded data from the line voltage input, wherein the processor block is arranged to control a first sampling rate that is associated with the analog-to-digital converter, wherein the first sampling rate is controlled such that the analog signal is down-converted as the under-sampled digital signal, wherein a digital signal processing algorithm is arranged to reject fundamental and harmonic frequencies that are associated with a power-line frequency that is associated with the line voltage input, anda second signal processing block being arranged to provide detection of a base-band signal from the under-sampled digital signal, the second signal processing block being arranged to provide the interface between he first signal processing block and the processor block, wherein the second signal processing block comprises a sampling block controlled to sample at a second sampling rate and a quadrature detector block, the second sampling rate being controlled by the processor block, the output of the second signal processing block corresponding to the digital bit stream, the second signal processing block being configured to detect the base-band signal by sampling a point ninety degrees apart from a carrier using the quadrature detector.

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