Endpoint event processing system

• US 7,432,824 B2
• Filed: 09/26/2006
• Issued: 10/07/2008
• Est. Priority Date: 07/24/2003
• Status: Expired due to Term

• Current Assignee: Hunt Techonologies Incorporated (Landis+Gyr Group AG)
• Original Assignee: Hunt Techonologies Incorporated (Landis+Gyr Group AG)
• Inventors: Flen, Rolf J., Haug, Stuart L., Ruohoniemi, Matthew David
• Primary Examiner(s): Edwards, Jr.; Timothy
• Application Number:
  US11/527,008
• Publication Number:
  US 20070018850A1
• Time in Patent Office: 742 Days
• Field of Search: 340/870.02, 340/870.11, 702/62, 714/776
• US Class Current: 340/870.02
• CPC Class Codes: G01D 4/002 Remote reading of utility meters
• CPC Class Codes: H02J 13/00007 using the power network as support for the transmission
• CPC Class Codes: H02J 13/00034 the elements or equipment being or involving an electric power substation
• CPC Class Codes: H04B 2203/5416 by adding signals to the wave form of the power source
• CPC Class Codes: H04B 2203/542 using zero crossing information
• CPC Class Codes: H04B 2203/5466 using three phases conductors
• CPC Class Codes: H04B 2203/5483 using coupling circuits
• CPC Class Codes: H04B 3/54 Systems for transmission via power distribution lines
• CPC Class Codes: Y02B 90/20 Smart grids as enabling technology in buildings sector smart grids supporting the management or operation of end-user stationary applications in general, or like technologies with no associated climate change mitigation effect Y04S20/00
• CPC Class Codes: Y04S 20/30 Smart metering, e.g. specially adapted for remote reading

Abstract

An endpoint processor includes a processor block, a timer block, a memory block, and analog-to-digital converter. The timer block is arranged to provide a time based signal to the processor block. The memory block cooperates with the processor block. The analog-to-digital converter is arranged to provide an interface between an analog signal and the processor block. The analog signal includes encoded data from a power signal. The processor block is arranged to control a sampling rate that is associated with the analog-to-digital converter such that the analog signal is down-converted as an under-sampled signal. The processor block is arranged to extract the encoded data from the down-converted signal by executing a digital signal processing algorithm that is stored in the memory block. The digital signal processing algorithm is arranged to reject fundamental and harmonic frequencies that are associated with a power-line frequency that is associated with the power signal.

Claims

1. An endpoint processor unit, comprising:

a processor block;

a timer block that is arranged to provide at least one time based signal to the processor block;

a memory block that is arranged to cooperate with the processor block;

a conditioning block that is arranged to provide input level control and signal filtering using an input level control block connected to an anti-aliasing filter block, the input level control block being arranged to receive a line voltage input from a power distribution line and the anti-aliasing filter block configured to output an attenuated line voltage signal, wherein the line voltage input being transformed prior to being input to the conditioning block, and

the anti-aliasing filtering block providing a band-pass filter, wherein a center frequency of the band-pass filter being centered on a modulation frequency; and

a processing block that is arranged to extract a digital bit stream from the line voltage input, the processing block comprising;

a first signal processing block being arranged to provide an under-sampled digital signal from an analog input, wherein the first signal processing block comprises an analog-to-digital converter, wherein the analog-to-digital converter being arranged to provide an interface between the attenuated line voltage signal and a second signal processing block, wherein the attenuated line voltage signal includes encoded data from the line voltage input, wherein the processor block is arranged to control a first sampling rate that is associated with the analog-to-digital converter, wherein the first sampling rate is controlled such that the analog signal is down-converted as the under-sampled digital signal, wherein a digital signal processing algorithm is arranged to reject fundamental and harmonic frequencies that are associated with a power-line frequency that is associated with the line voltage input, and

a second signal processing block being arranged to provide detection of a base-band signal from the under-sampled digital signal, the second signal processing block being arranged to provide the interface between he first signal processing block and the processor block, wherein the second signal processing block comprises a sampling block controlled to sample at a second sampling rate and a quadrature detector block, the second sampling rate being controlled by the processor block, the output of the second signal processing block corresponding to the digital bit stream, the second signal processing block being configured to detect the base-band signal by sampling a point ninety degrees apart from a carrier using the quadrature detector.

2. The endpoint processor unit of claim 1, wherein the processor block being configured to execute a second digital signal processing algorithm that is stored in the memory block, the second digital signal processing algorithm being configured to use a frequency shift keying scheme.

3. The endpoint processor unit of claim 1, wherein the first sampling rate is controlled such that the analog signal is down-converted as the under-sampled digital signal further comprises the first sampling rate being controlled using a frequency looked loop system.

4. The endpoint processor unit of claim 1, wherein the anti-aliasing filter block configured to output the attenuated line voltage signal comprises the anti-aliasing filter block buffering the attenuated line voltage signal.

5. The method of claim 4, wherein recording the usage data received from the mechanism into the time-of-use map further comprises recording the usage data received from the metering mechanism into the time-of-use map, wherein the time-of-use map comprises a plurality of selectable time-of-use maps further comprises recording the usage data received from the metering mechanism into the time-of-use map, wherein the time of user map comprises the plurality of selectable time-of-use maps, the selection o each of the plurality of selectable time-of-use maps being based on at least one of the following:

a consumer type, a holiday schedule, an override command, and a scheduled event.

6. A method for event processing in an endpoint, comprising:

executing an idle function while waiting for an event;

detecting a trigger for the event;

evaluating the event after the trigger is detected;

processing a received packet when the event corresponds to a received packet detection;

recording at least one metering parameter when the event corresponds to a scheduled recording cycle, wherein the scheduled recording cycle corresponds to a usage data received from a metering mechanism, wherein recording the at least one metering parameter comprises recording the usage data received from the metering mechanism into a time-of-use map, the time-of-use map being organized according to a day type and the recorded usage data from the metering mechanism being stored into one of a plurality of pre-defined intervals corresponding to a portion of a day;

formatting a packet for transmission when the event corresponds to a scheduled reporting cycle;

starting a packet transmission after formatting the at least one packet for transmission; and

wherein formatting a packet for transmission corresponds to formatting a packet according to a protocol, wherein the protocol includes a asynchronous flag field, a health flag field, a payload field, and an error check and detection field, wherein the payload field is defined by a predetermined sequence when the asynchronous flag field is not set, and wherein the payload field is flexibly defined when the asynchronous flag field is set.

7. The method of claim 6, wherein recording the usage data received from the metering mechanism into the time-of-use map further comprises recording the usage data received from the metering mechanism into the time-of-use map further comprises recording the usage data received from the metering mechanism into the time-of-use map, wherein the time-of-use map comprises a plurality of selectable time-of-use maps.

8. A method for event processing in an endpoint, comprising:

executing as idle function while waiting for as event;

detecting a trigger for the event;

evaluating the event after the trigger is detected;

processing a received packet when the event corresponds to a received packet detection;

recording a least one metering parameter when the event corresponds to a scheduled recording cycle, wherein recording the at least one metering parameter comprises recording a usage data received from a metering mechanism into a time-of-use map, he time-of-use map being organized according to a day type and the recorded usage data received from the metering mechanism being stored into one of a plurality of pre-defined time intervals corresponding to a portion of a day;

formatting a packet for transmission when the event corresponds to a scheduled reporting cycle;

starting a packet transmission after formatting the at least one packet for transmission; and

selecting a packet sequence number based on a current day of the week, and wherein forming the packet for transmission includes organizing a packet payload according to the selected packet sequence number.

9. The endpoint processor unit of claim 8, wherein the processor block being configured to execute the second digital processing algorithm is further configured to use a non-return to zero (NRZI) frequency shift keying scheme.