Drive for active matrix cholesteric liquid crystal display

• US 7,432,895 B2
• Filed: 10/02/2003
• Issued: 10/07/2008
• Est. Priority Date: 10/02/2003
• Status: Active Grant

• Current Assignee: Iris Optronics Co., Ltd.
• Original Assignee: Industrial Technology Research Institute
• Inventors: Mi, Xiang-Dong
• Primary Examiner(s): DHARIA, PRABODH M
• Application Number:
  US10/677,764
• Publication Number:
  US 20050073491A1
• Time in Patent Office: 1,832 Days
• Field of Search: 345 87- 89, 345/50, 345/32, 345/591, 345691-696, 345/100, 345 94- 98, 345/204, 345/214, 345/107, 345/82, 345/581, 313/310, 313/495, 349/109, 315/169.3, 445/24, 709/224
• US Class Current: 345/87
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 3/3651 using multistable liquid crystals, e.g. ferroelectric liquid crystals

Abstract

A method of driving an active matrix cholesteric liquid crystal display that includes a matrix of data and select lines and an array of pixels connected to the data and select lines through active switching elements, a pixel being capable of producing two or more gray levels includes providing a select voltage and a plurality of data voltages, and during a pixel writing cycle, applying the select voltage and the data voltages to the select and data lines of the display to produce only three pixel voltage levels 0, +U and −U, having respective duty cycles and controlling the duty cycles of the pixel voltage levels to determine the gray levels of the pixels, and wherein the average voltage applied to a pixel during the pixel writing cycle is zero.

Claims

1. A method of driving an active matrix cholesteric liquid crystal display that includes a matrix of data and select lines and an array of pixels connected to the data and select lines through active switching elements, a pixel being capable of producing two or more gray levels, comprising:

a) providing a select voltage and a plurality of data voltages; and

b) during a pixel writing cycle, applying the select voltage and the data voltages to the select and data lines of the display to produce only three pixel voltage levels 0, +U and −

U, having respective duty cycles and controlling the duty cycles of the pixel voltage levels to determine the gray levels of the pixels, and wherein the average voltage applied to a pixel during the pixel writing cycle is zero.

2. The method claimed in claim 1, wherein the data voltage levels consist of a zero voltage and a non-zero voltage U.

3. The method claimed in claim 2, wherein the active matrix liquid crystal display further includes a common electrode connected to all of the pixels, and further comprising the step of applying the zero voltage to the common electrode and the voltage U to the data line to generate the pixel voltage U, and applying the voltage U to the common electrode and the voltage to the data line to generate the pixel voltage −

U.

4. The method claimed in claim 1, wherein the data voltage levels consist of a zero voltage and two non-zero voltages +U and −

U.

5. The method claimed in claim 4, wherein the active matrix liquid crystal display further includes a common electrode connected to all of the pixels, and further comprising the step of applying the zero voltage to the common electrode.

6. The method claimed in claim 1, wherein a pixel writing cycle includes:

a) a selection portion wherein a non zero pixel voltage is applied to any pixels in the display whose state is to be changed; and

b) a duty cycle portion wherein the duty cycle of the non zero pixel voltages are determined.

7. An active matrix cholesteric liquid crystal display, comprising:

a) an array of pixels each capable of producing two or more gray levels and a corresponding array of active switching elements;

b) a matrix of data and select lines connected to the pixels through the active switching elements; and

c) a driver for applying a select voltage and one of a plurality of data voltages to the select and data lines of the display to produce only three pixel voltage levels 0, +U and −

U, having respective duty cycles and controlling the duty cycles of the pixel voltage levels to determine the gray levels of the pixels.

8. The display claimed in claim 7, wherein the data voltage levels consist of a zero voltage and a non-zero voltage U.

9. The display claimed in claim 8, further comprising a common electrode connected to all of the pixels, and wherein the driver applies the zero voltage to the common electrode and the voltage U to the data line to generate the pixel voltage U, and applies the voltage U to the common electrode and the voltage to the data line to generate the pixel voltage −

U.

10. The display claimed in claim 7, wherein the data voltage levels consist of a zero voltage and two non-zero voltages +U and −

U.

11. The display claimed in claim 10, wherein the active matrix liquid crystal display further includes a common electrode connected to all of the pixels, and wherein the zero voltage is applied to the common electrode.

12. The display claimed in claim 7, wherein the driver drives the pixels during a pixel writing cycle that includes:

a) a selection portion wherein a non zero pixel voltage is applied to any pixels in the display whose state is to be changed; and

b) a duty cycle portion wherein the duty cycle of the non zero pixel voltages are determined.