Multiple select gates with non-volatile memory cells

• US 7,433,231 B2
• Filed: 04/26/2006
• Issued: 10/07/2008
• Est. Priority Date: 04/26/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Primary Examiner(s): Ho; Hoai V
• Application Number:
  US11/411,376
• Publication Number:
  US 20070253253A1
• Time in Patent Office: 895 Days
• Field of Search: 365/185.03, 365/185.17, 365/185.24
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer.

Claims

1. A memory array, comprising:

a number of non-volatile memory cells;

a number of select gates coupled in series to the number of non-volatile memory cells;

wherein a first select gate includes a control gate and a floating gate electrically connected together by a conductive strap through a dielectric layer; and

wherein a second select gate includes a control gate and a floating gate which are electrically coupled but separated by a dielectric layer.

2. The array of claim 1, wherein the second select gate is adjacent the number of non-volatile memory cells.

3. The array of claim 1, wherein the second select gate has a threshold voltage which is substantially the same as a threshold voltage for each of the number of non-volatile memory cells.

4. The array of claim 1, wherein the number of non-volatile memory cells includes a number of non-volatile memory cells coupled in series.

5. The array of claim 1, wherein the number of non-volatile memory cells includes a NAND string.

6. A memory array, comprising:

a NAND string of non-volatile memory cells;

a number of source select gates on a source side of the string;

a drain select gate on a drain side of the string; and

wherein the number of source select gates includes at least one source select gate having a control gate and a floating gate electrically connected together by a conductive strap through a dielectric layer, and includes at least one source select gate having a control gate and a floating gate which are electrically separated by a dielectric layer.

7. The array of claim 6, wherein at least one of the number of source select gates has a pitch that is substantially equal to a pitch of each non-volatile memory cell in the NAND string.

8. The array of claim 6, wherein the array includes a pair of series coupled source select gates on the source side of the NAND string, and a pair of series coupled drain select gates on the drain side of the NAND string.

9. The array of claim 6, wherein the at least one source select gate having the control gate and the floating gate which are electrically separated by the dielectric layer has a cell structure which is substantially the same as a cell structure for each non-volatile memory cell in the NAND string.

10. The array of claim 6, wherein the at least one source select gate having the control gate and the floating gate which are electrically separated by the dielectric layer has a threshold voltage which is substantially the same as a threshold voltage for each non-volatile memory cell in the NAND string.

11. A memory array, comprising:

a string of non-volatile memory cells;

a number of source select gates on a source side of the string and coupled in series with the string;

a number of drain select gates on a drain side of the string and coupled in series with the string; and

wherein at least one select gate on a cell side of the string has a control gate and a floating gate electrically separated by a dielectric layer from one another and is coupled in series with at least one select gate having a control gate and a floating gate which are electrically connected by a conductive strap through a dielectric layer.

12. The memory array of claim 11, wherein a threshold voltage of the at least one select gate on the cell side of the string is substantially the same as a threshold voltage for each non-volatile memory cell of the string.

13. The memory array of claim 11, wherein the string of-non-volatile memory cells is a NAND string.

14. The memory array of claim 11, wherein the at least one select gate on the cell side is substantially the same size as each non-volatile memory cell of the string.

15. A memory device, comprising:

an array of non-volatile memory cells including a string of non-volatile memory cells;

circuitry for control and access to the array of non-volatile memory cells;

wherein the array of non-volatile memory cells includes;

a first number of select gates coupled to a source side of the string of non-volatile memory cells, wherein a first one of the first number of select gates is coupled to a source line and has a control gate and a floating gate electrically connected together by a conductive strap through a dielectric layer, and wherein a second one of the first number of select gates is coupled to a first one of the string of non-volatile memory cells and has a control gate and a floating gate electrically separated by a dielectric layer from one another; and

a second number of select gates coupled to a drain side of the string of non-volatile memory cells, and wherein a last one of the second number of select gates is coupled to a bit line.

16. The memory device of claim 15, wherein:

the second number of select gates includes a pair of select gates series coupled to the drain side of the string, and coupled to a single drain select line;

the first one of the first number of select gates is coupled to a first source select line; and

the second one of the first number of select gates is coupled to a second source select line.

17. The memory device of claim 15, wherein the second one of the first number of select gates has a gate length which is substantially equivalent to a gate length of each non-volatile memory cell in the string.

18. A memory module, comprising:

a number of contacts;

two or more memory devices, each having access lines selectively coupled to the number of contacts; and

wherein at least one of the memory devices includes;

an array of non-volatile memory cells including a string of non-volatile memory cells;

circuitry for control and access to the array of non-volatile memory cells;

wherein the array of non-volatile memory cells includes;

a pair of source select gates series coupled to the string, wherein a first one of the source select gates has a control gate and a floating gate electrically connected together by a conductive strap through a dielectric layer, and wherein a second one of the source select gates has a control gate and a floating gate which are separated by a dielectric; and

a pair of drain select gates series coupled to the string.

19. An electronic system, comprising:

a processor, and

a memory device coupled to the processor, wherein the memory device includes;

an array of non-volatile memory cells including a NAND string;

circuitry for control and access to the array of non-volatile memory cells; and

wherein the ray of non-volatile memory cells includes;

a first and a second source select gate series connected to the NAND string, wherein;

the first source select gate has a control gate and a floating gate which are electrically connected by a conductive strap through a dielectric layer; and

the second source select gate has a control gate and a floating gate separated by a dielectric, and has a threshold voltage and a cell size which are substantially equal to a threshold voltage and a cell size of each non-volatile memory cell in the NAND string; and

a drain select gate connected to the NAND string, the drain select gate has a control gate and a floating gate which are electrically connected by a conductive strap through a dielectric layer.

20. The electronic system of claim 19, wherein a threshold voltage of the first source select gate is different from the threshold voltage of the second source select gate.

21. The electronic system of claim 19, wherein the system includes a first and a second drain select gate series connected to the NAND string, wherein:

the first drain select gate has a control gate and a floating gate which are electrically connected by a conductive strap through a dielectric layer; and

the second drain select gate has a control gate and a floating gate separated by a dielectric, and has a threshold voltage and a cell size which are substantially equal to a threshold voltage and a cell size of each non-volatile memory cell in the NAND string.