NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

• US 7,433,233 B2
• Filed: 06/18/2007
• Issued: 10/07/2008
• Est. Priority Date: 12/31/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Fasoli, Luca G., Nallamothu, Sucheta, Walker, Andrew J., Chen, En-Hsing, Ilkbahar, Alper
• Primary Examiner(s): Pham; Ly D
• Application Number:
  US11/764,793
• Publication Number:
  US 20070242511A1
• Time in Patent Office: 477 Days
• Field of Search: 365/185.02, 365/185.17, 365/185.18, 365/185.23, 365/185.28, 365/185.29, 365/230.03
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 51/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

Claims

1. A method of operating an integrated circuit having a three-dimensional memory array including at least two planes of memory cells, said memory cells comprising thin film switch devices having a charge storage dielectric and which cells are arranged in a plurality of series-connected NAND strings, said method comprising the steps of:

biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage; and

then

capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell;

wherein the biasing step comprises;

(a) conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string;

(b) coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string; and

(c) turning on the half-selected memory cell and any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string, said turning on step comprising driving the word lines associated with any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string to a first passing voltage sufficient to turn on both programmed and unprogrammed memory cells to bias the half-selected memory cell channel to the first voltage; and

then

(d) decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage, said decoupling step comprising driving the unselected word lines associated with the unselected NAND string to a second passing voltage different than the first passing voltage, said second passing voltage chosen such that both programmed and unprogrammed memory cells in the unselected NAND string are turned off, and such that voltage stress across unselected memory cells in a selected NAND string is reduced.

2. The method of claim 1 wherein step (d) further comprises driving to ground a word line associated with at least one unselected memory cell adjacent to the half-selected memory cell.

3. The method of claim 1 wherein step (c) further comprises driving the word line associated with the half-selected memory cell to the first passing voltage.

4. The method of claim 3 wherein the first voltage is substantially equal to the bit line inhibit voltage.

5. The method of claim 3 wherein the first voltage is substantially less than the bit line inhibit voltage.

6. The method of claim 3 wherein step (c) further comprises driving all word lines associated with memory cells of the unselected NAND string to the first passing voltage.

7. The method of claim 1 wherein word lines driven to the second passing voltage are driven directly from the first passing voltage to the second passing voltage.

8. The method of claim 1 wherein word lines driven to the second passing voltage are driven first from the first passing voltage to ground, and then driven to the second passing voltage.

9. The method of claim 1 further comprising:

(e) coupling a first end of a selected NAND string of the selected memory block through a first group of at least one series selection device, to a respective first array line associated with the selected NAND string, said respective first array line conveying a bit line programming voltage; and

(f) coupling the bit line programming voltage to a channel region of a selected memory cell in the selected NAND string, said selected memory cell also associated with the selected word line.

22. The method as recited in claim 1 wherein:

the second passing voltage is less than the sum of the bit line inhibit voltage and a threshold voltage corresponding to an erased memory cell.

23. The method as recited in claim 1 wherein:

the difference in magnitude between the second passing voltage and the first passing voltage is greater than the maximum threshold difference between programmed and erased memory cells.

24. The method of claim 4 wherein:

the first passing voltage is greater than the bit line inhibit voltage; and

the second passing voltage is less than the bit line inhibit voltage.

10. A method of operating an integrated circuit having a memory array including at least one plane of memory cells, said memory cells comprising switch devices having a charge storage dielectric and which cells are arranged in a plurality of series-connected NAND strings, said method comprising the steps of:

biasing a channel region of a half-selected memory cell in an unselected NAND string of a selected memory block, to a first voltage; and

then

capacitively coupling the channel region to a second voltage different than the first voltage when a selected word line associated with the half-selected memory cell transitions to a word line programming voltage, to thereby reduce a voltage potential between the selected word line and the channel region of the half-selected memory cell;

wherein the biasing step comprises;

(a) conveying a bit line inhibit voltage on a respective first array line associated with the unselected NAND string;

(b) coupling a first end of the unselected NAND string through a first group of at least one series selection device, to the respective first array line associated with the unselected NAND string; and

(c) turning on the half-selected memory cell and any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string; and

then

(d) decoupling the channel region of the half-selected memory cell from the respective first array line after establishing the half-selected memory cell channel region to the first voltage; and

wherein step (d) comprises turning off at least one device within the first group of at least one series selection device of the unselected NAND string.

11. The method of claim 10 wherein:

step (c) comprises driving the word lines associated with any intervening memory cells between the half-selected memory cell and the first end of the NAND string to a first passing voltage sufficient to turn on both programmed and unprogrammed memory cells to bias the half-selected memory cell channel to the first voltage; and

step (d) comprises driving the unselected word lines associated with any intervening memory cells between the half-selected memory cell and the first end of the unselected NAND string to a second passing voltage different than the first passing voltage, said second passing voltage chosen such that both programmed and unprogrammed memory cells in the unselected NAND string are turned off, and such that voltage stress across unselected memory cells in a selected NAND string is reduced.

12. The method of claim 11 wherein step (c) further comprises driving all word lines associated with memory cells of the unselected NAND string to the first passing voltage.

13. The method of claim 11 wherein word lines driven to the second passing voltage are driven directly from the first passing voltage to the second passing voltage.

14. The method of claim 11 wherein word lines driven to the second passing voltage are driven first from the first passing voltage to ground, and then driven to the second passing voltage.

15. The method of claim 11 wherein:

the first passing voltage is greater than the bit line inhibit voltage; and

the second passing voltage is less than the bit line inhibit voltage.

16. The method as recited in claim 11 wherein:

the second passing voltage is less than the sum of the bit line inhibit voltage and a threshold voltage corresponding to an erased memory cell.

17. The method as recited in claim 16 wherein:

the second passing voltage is substantially equal to ground.

18. The method as recited in claim 11 wherein:

the difference in magnitude between the second passing voltage and the first passing voltage is greater than the maximum threshold difference between programmed and erased memory cells.

19. The method of claim 11 further comprising:

repeating the biasing and coupling steps for a given half-selected memory cell to provide a plurality of programming pulses and to re-establish a voltage bias of the half-selected memory cell channel region before each such programming pulse.

20. The method of claim 11 further comprising:

coupling a first end of a selected NAND string of the selected memory block through a first group of at least one series selection device, to a respective first array line associated with the selected NAND string, said respective first array line conveying a bit line programming voltage;

coupling the bit line programming voltage to a channel region of a selected memory cell in the selected NAND string, said selected memory cell also associated with the selected word line; and

driving unselected word lines associated with memory cells between the selected memory cell and the second end of the selected NAND string to a third passing voltage closer to the bit line programming voltage than is the second passing voltage at least during any selected word line programming pulse, to thereby reduce programming stress across such unselected memory cells.

21. The method of claim 20 wherein:

the third passing voltage is substantially equal to ground.