Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data

• US 7,433,241 B2
• Filed: 12/29/2006
• Issued: 10/07/2008
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Lutze, Jeffrey W., Hemink, Gerrit Jan, Dong, Yingda, Lee, Dana
• Primary Examiner(s): Lam; David
• Application Number:
  US11/618,580
• Publication Number:
  US 20080159002A1
• Time in Patent Office: 648 Days
• Field of Search: 365/185.25, 365/185.17, 365/185.18, 365/203, 365/185.22, 365/185.28, 365/185.29, 365/185.03
• US Class Current: 365/185.25
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at higher voltages for certain memory cells that may have undergone partial programming.

Claims

1. A method performed as part of programming non-volatile storage, comprising:

pre-charging a group of unselected non-volatile storage elements prior to applying a program signal to a particular non-volatile storage element of said group, said group includes a first set of one or more non-volatile storage elements on a drain side of said group with respect to said particular non-volatile storage element and a second set of two or more non-volatile storage elements, said first set has been subjected to partial programming, said pre-charging includes applying one or more first pre-charge enable signals to said first set of one or more non-volatile storage elements and applying one or more second pre-charge enable signals to said second set of two or more non-volatile storage elements, said one or more first pre-charge enable signals are at higher voltages than said one or more second pre-charge enable signals; and

applying said program signal to said particular non-volatile storage element after pre-charging said group of unselected non-volatile storage elements.

2. The method of claim 1, wherein:

pre-charging said group further includes applying a pre-charge voltage to a bit line for said group of unselected non-volatile storage elements.

3. The method of claim 1, wherein:

said second set of two or more non-volatile storage elements has not been subjected to partial programming prior to said pre-charging.

4. The method of claim 1, wherein:

said second set of two or more non-volatile storage elements includes a first subset of one or more non-volatile storage elements that has not been subjected to partial programming and a second subset of one or more non-volatile storage elements that has completed programming.

5. The method of claim 1, wherein:

said particular non-volatile storage element is connected to a targeted word line;

said targeted word line is connected to a selected non-volatile storage element of a different group of non-volatile storage elements that is intended to be programmed.

6. The method of claim 1, wherein:

said first set of one or more non-volatile storage elements only includes a first non-volatile storage element that is adjacent to said particular storage element.

7. The method of claim 1, wherein:

said first set of one or more non-volatile storage elements includes a first non-volatile storage element that is adjacent to said particular non-volatile storage element and a second non-volatile storage element that is adjacent to said first non-volatile storage element.

8. The method of claim 1, wherein:

said group of unselected non-volatile storage elements is part of a NAND string having a bit line side and a source line side, said bit line side corresponds to said drain side;

said steps of pre-charging and applying are part of a programming process that applies said program signal in an order that begins with a non-volatile storage element adjacent to a select gate at said source line side and ends with a non-volatile storage element adjacent to a select gate at said bit line side; and

said first set of one or more non-volatile storage elements is on said bit line side with respect to said particular non-volatile storage element.

9. The method of claim 8, wherein:

said second set of two or more non-volatile storage elements is on said source line side with respect to said particular non-volatile storage element.

10. The method of claim 8, wherein:

said second set of two or more non-volatile storage elements includes a first subset of one or more non-volatile storage elements on said bit line side with respect to said particular non-volatile storage element and a second subset of one or more non-volatile storage elements on said source line side with respect to said particular non-volatile storage element.

11. The method of claim 8, wherein:

said particular non-volatile storage element is said non-volatile storage element that is adjacent to said select gate at said source line side.

12. The method of claim 8, wherein:

said particular non-volatile storage element is adjacent to said non-volatile storage element that is adjacent to said select gate at said bit line side; and

said particular non-volatile storage element is on said source line side with respect to said non-volatile storage element that is adjacent to said select gate at said bit line side.

13. The method of claim 1, further comprising:

boosting said group of unselected non-volatile storage elements after said pre-charging, said boosting includes applying one or more first boosting signals to said first set of one or more non-volatile storage elements and applying one or more second boosting signals to said second set of two or more non-volatile storage elements.

14. The method of claim 13, wherein:

said one or more first boosting signals are at higher voltages than said one or more second boosting signals.

15. The method of claim 13, wherein:

said one or more first boosting signals are at voltages equal to voltages of said one or more second boosting signals.

16. The method of claim 1, wherein:

said one or more first pre-charge enable signals are applied to control gates of said first set of one or more non-volatile storage elements; and

said one or more second pre-charge enable signals are applied to control gates of said second set of two ore more non-volatile storage elements.

17. The method of claim 1, wherein:

said program signal is part of a series of voltage pulses that increase in magnitude.

18. The method of claim 1, wherein:

said unselected non-volatile storage elements of said group are flash memory cells.

19. The method of claim 1, wherein:

said unselected non-volatile storage elements of said group are multi-state flash memory cells.

20. A method of operating non-volatile storage, comprising:

subjecting a first subset of a set of non-volatile storage elements to partial programming;

subjecting a second subset of said set of non-volatile storage elements to partial programming after subjecting said first subset to partial programming;

completing programming of said first subset after subjecting said second subset to partial programming; and

pre-charging unselected groups of non-volatile storage elements of said set as part of said completing programming of said first subset, said pre-charging includes applying a first voltage to said second subset and applying a second voltage to a third subset of said set of non-volatile storage elements while applying said first voltage, said second voltage is less than said first voltage.

21. A method performed as part of programming non-volatile storage, comprising:

applying a pre-charge voltage to a group of non-volatile storage elements having a bit line side and a source line side;

applying a first voltage to a first set of one or more non-volatile storage elements of said group while applying said pre-charge voltage, said first set is on said bit line side with respect to a particular non-volatile storage element of said group and has been subjected to partial programming;

applying a second voltage to a second set of two or more non-volatile storage elements of said group while applying said pre-charge voltage, said second voltage is lower than said first voltage;

applying a program voltage to said particular non-volatile storage element of said group;

applying a third voltage to said first set while applying said program voltage, said third voltage is different from said first voltage; and

applying a fourth voltage to said second set while applying said program voltage, said fourth voltage is different from said second voltage.

22. The method of claim 21, wherein:

said first voltage is a first pre-charge enable voltage;

said second voltage is a second pre-charge enable voltage;

said third voltage is a first boosting voltage; and

said fourth voltage is a second boosting voltage.

23. The method of claim 22, further comprising:

applying a third boosting voltage to said particular non-volatile storage element before applying said program voltage.

24. The method of claim 23, further comprising:

applying a third pre-charge enable voltage to said particular non-volatile storage element before applying said third boosting voltage, wherein applying said third pre-charge enable voltage is performed while applying said pre-charge voltage.

25. The method of claim 24, wherein:

said third boosting voltage is equal to said second boosting voltage; and

said third pre-charge enable voltage is equal to said second pre-charge enable voltage.

26. The method of claim 21, wherein:

applying said pre-charge voltage to said group comprises applying a program inhibit voltage to a bit line of said group.

27. The method of claim 21, wherein:

said group of non-volatile storage elements is part of an unselected NAND string;

said particular non-volatile storage element is an unselected non-volatile storage element connected to a targeted word line for said unselected NAND string, said unselected non-volatile storage element is to be inhibited from programming while applying said program voltage to said targeted word line; and

said targeted word line is also connected to a selected non-volatile storage element of a selected NAND string, said selected non-volatile storage element is to be programmed while applying said program voltage to said targeted word line;

said first set of one or more non-volatile storage elements of said group are connected to a first set of one or more unselected word lines for said unselected NAND string and said selected NAND string; and

said second set of two or more non-volatile storage elements of said group is connected to a second set of two or more unselected word lines for said unselected NAND string and said selected NAND string.

28. A method of operating non-volatile storage, comprising:

applying a first pre-charge enable voltage to a first unselected word line for a set of NAND strings, said first unselected word line is next to a selected word line for said set of NAND strings, said first unselected word line is subjected to partial programming after subjecting said selected word line to partial programming but prior to completing programming for said selected word line;

applying one or more different pre-charge enable voltages to a set of one or more other unselected word lines for said set of NAND strings;

applying a pre-charge voltage to unselected NAND strings of said set while applying said first pre-charge enable voltage and said one or more different pre-charge enable voltages, wherein applying said pre-charge voltage, said first pre-charge enable voltage and said one or more different pre-charge enable voltages causes at least a portion of said unselected NAND strings to be pre-charged; and

applying a program voltage to said selected word line while applying one or more boosting voltages to at least a portion of said other unselected word lines.

29. The method of claim 28, wherein:

said pre-charge voltage is a program inhibit voltage.

30. The method of claim 28, further comprising:

applying said first pre-charge enable voltage to a second unselected word line for said set of NAND strings, said second unselected word line is adjacent to said first unselected word line.

31. The method of claim 28, wherein:

said one or more different pre-charge enable voltages are lower than said first pre-charge enable voltage.

32. A method of operating non-volatile storage, comprising:

erasing a plurality of non-volatile storage elements;

subjecting a first subset of non-volatile storage elements to partial programming after erasing said plurality of non-volatile storage elements;

subjecting a second subset of non-volatile storage elements to partial programming after subjecting said first subset of non-volatile storage elements to partial programming;

completing programming of said first subset after subjecting said second subset to partial programming;

pre-charging unselected groups of non-volatile storage elements of said plurality as part of said completing programming of said first subset of non-volatile storage elements, said pre-charging includes applying a first voltage to said second subset and applying a second voltage to a third subset of non-volatile storage elements while applying said first voltage, said second voltage is less than said first voltage; and

boosting said groups of non-volatile storage elements as part of said completing programming after said pre-charging, said boosting includes applying a third voltage to said second subset while applying a program voltage to said first subset.

33. The method of claim 32, wherein said boosting further includes:

applying a fourth voltage to said third subset while applying said third voltage to said second subset and applying said program voltage to said first subset.

34. The method of claim 33, wherein said boosting further includes:

applying said fourth voltage to said first subset prior to applying said program voltage;

applying said third voltage to said second subset while applying said fourth voltage to said first subset; and

applying said fourth voltage to said third subset while applying said fourth voltage to said first subset.