Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device

• US 7,433,252 B2
• Filed: 11/04/2005
• Issued: 10/07/2008
• Est. Priority Date: 11/11/2004
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chu, Yong-Gyu, Byun, Sang-Man, Park, Seok-Ho, Kim, Gyu-Yeol
• Primary Examiner(s): Hur; J. H.
• Assistant Examiner(s): King; Douglas
• Application Number:
  US11/267,203
• Publication Number:
  US 20060098506A1
• Time in Patent Office: 1,068 Days
• Field of Search: 365/201, 365/189.17, 365/189.16, 324/754, 714/720, 714/718, 714/719
• US Class Current: 365/201
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array.

Claims

1. A method of electrically testing a semiconductor memory device, comprising:

dividing a plurality of data input/output pads into a plurality of data input/output groups;

coupling a control signal generation pad to the data input/output pads;

outputting a control signal through the control signal generation pad;

enabling at least one data input/output pad of each data input/output group in response to the control signal;

writing non-identical data bits to neighboring memory cells of a memory cell array through the enabled data input/output pads; and

reading out the written data from the memory cell array.

2. The method of claim 1, further comprising connecting the plurality of data input/output pads of each group to one input/output (I/O) channel of a tester.

3. The method of claim 1, wherein the semiconductor memory device comprises 2N (N is a natural number) data input/output pads.

4. The method of claim 1, wherein outputting the control signal through the control signal generation pad comprises outputting the control signal from a data input multiplexer (DINMUX) included in the semiconductor memory device that is coupled to the control signal generation pad.

5. The method of claim 1, wherein writing the data bits to the memory cells of the memory cell array through the enabled data input/output pads comprises separately enabling each data input/output pad of one of the data input/output groups according to a frequency of toggling of the control signal.

6. The method of claim 1, wherein in the test for the writing function of the memory cell array, writing of data to 2m (m is a natural number) memory cells is tested.

7. The method of claim 6, wherein the control signal generation pad is a control pin for the semiconductor memory device not used in the writing of data to the 2m memory cells outside of the test for the writing function of the memory cell array.

8. The method of claim 1, wherein the test for the writing function of the memory cell array is included in an electrical die sort (EDS) test.

9. The method of claim 1, wherein the test mode for the writing function of the memory cell array is included in a final test.

10. The method of claim 1, wherein the control signal generation pad is a no-connect (NC) pad.

11. The method of claim 1, wherein outputting the control signal comprises:

generating at least one pulse over a plurality of time intervals as the control signal;

wherein for each data input/output group, each of the data input/output pads of the group are enabled in response to a different sequence of the least one pulse over the time intervals.

12. The method of claim 1, wherein coupling the control signal generation pad to the data input/output pads comprises coupling the control signal generation pad to the data input/output pads through probe needles of a tester used in the testing of the semiconductor memory device.