Processing architecture for a reconfigurable arithmetic node
First Claim
1. A reconfigurable arithmetic node (RAN) in an adaptive computing system configurable to execute any one of a plurality of target algorithms, wherein the target algorithms include an Asymmetric FIR filter, a Symmetric FIR Filter, a Complex Multiply FIR Filter, a Sum-of-absolute-differences, a Bi-linear interpolation, a Bi-quad IIR filter, a Radix-2 Fast Fourier Transform/Inverse Fast Fourier Transform, a Radix -2 Discrete Cosine Transform/Inverse Discrete Cosign Transform, a Golay Correlator, and a Local Oscillator/Mixer, the RAN comprising an execution unit having:
- a program control unit (PCU) for controlling task set-up and tear down in the RAN for execution of the one target algorithm;
an algorithm control unit (ACU) for controlling a data path unit and generating a control sequence associated with the one target algorithm of the plurality of algorithms and an address generator unit to selected and enable execution of the one target algorithm; and
a finite state machine for receiving control signals to execute one of the target algorithms and for selecting between the PCU and the ACU to execute the one target algorithm.
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Abstract
A computational unit, or node, in a adaptable computing system is described. A preferred embodiment of the node allows the node to be adapted for use for any of ten types of functionality by using a combination of execution units with a configurable interconnection scheme. Functionality types include the following: Asymmetric Finite Impulse Response (FIR) Filter, Symmetric FIR Filter, Complex Multiply/FIR Filter, Sum-of-absolute-differences, Bi-linear Interpolation, Biquad Infinite Impulse Response (IIR) Filter, Radix-2 Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT), Radix-2 Discrete Cosign Transform (DCT)/Inverse Discrete Cosign Transform (IDCT), Golay Correlator, Local Oscillator/Mixer.
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Citations
18 Claims
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1. A reconfigurable arithmetic node (RAN) in an adaptive computing system configurable to execute any one of a plurality of target algorithms, wherein the target algorithms include an Asymmetric FIR filter, a Symmetric FIR Filter, a Complex Multiply FIR Filter, a Sum-of-absolute-differences, a Bi-linear interpolation, a Bi-quad IIR filter, a Radix-2 Fast Fourier Transform/Inverse Fast Fourier Transform, a Radix -2 Discrete Cosine Transform/Inverse Discrete Cosign Transform, a Golay Correlator, and a Local Oscillator/Mixer, the RAN comprising an execution unit having:
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a program control unit (PCU) for controlling task set-up and tear down in the RAN for execution of the one target algorithm; an algorithm control unit (ACU) for controlling a data path unit and generating a control sequence associated with the one target algorithm of the plurality of algorithms and an address generator unit to selected and enable execution of the one target algorithm; and a finite state machine for receiving control signals to execute one of the target algorithms and for selecting between the PCU and the ACU to execute the one target algorithm. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An adaptive computer comprising a plurality of reconfigurable arithmetic nodes coupled together by a matrix interconnection network for transferring data control and configuration information between and among the reconfigurable arithmetic nodes, each of the nodes comprising a reconfigurable arithmetic node (RAN) configurable to execute any one of a plurality of target algorithms, wherein the target algorithm include an Asymmetric FIR filter, a Symmetric FIR Filter, a Complex Multiply FIR Filter, a Sum-of-absolute-differences, a Bi-linear interpolation, a Bi-quad IIR filter, a Radix-2 Fast Fourier Transform/Inverse Fast Fourier Transform, a Radix -2 Discrete Cosine Transform/Inverse Discrete Cosine Transform, a Golay Correlator, and a Local Oscillator/Mixer, the RAN comprising an execution unit having:
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a program control unit (PCU) for controlling task set-up and tear down in the RAN for execution of the one target algorithm; an algorithm control unit (ACU) for controlling a data path unit and generating a control sequence associated with the one targeted algorithm of the plurality of target algorithms and an address generator unit to enable execution of a specific one of the target algorithms; and a finite state machine for receiving control signals to execute one of the target algorithms and for selecting between the PCU and the ACU to execute the one target algorithm. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification