Processing architecture for a reconfigurable arithmetic node

• US 7,433,909 B2
• Filed: 05/21/2003
• Issued: 10/07/2008
• Est. Priority Date: 06/25/2002
• Status: Active Grant

• Current Assignee: QST Holdings LLC
• Original Assignee: NVIDIA Corporation
• Inventors: Scheuermann, W. James
• Primary Examiner(s): Mai; Tan V.
• Application Number:
  US10/443,596
• Publication Number:
  US 20040030736A1
• Time in Patent Office: 1,966 Days
• Field of Search: 708/400, 708/300
• US Class Current: 708/400
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A computational unit, or node, in a adaptable computing system is described. A preferred embodiment of the node allows the node to be adapted for use for any of ten types of functionality by using a combination of execution units with a configurable interconnection scheme. Functionality types include the following: Asymmetric Finite Impulse Response (FIR) Filter, Symmetric FIR Filter, Complex Multiply/FIR Filter, Sum-of-absolute-differences, Bi-linear Interpolation, Biquad Infinite Impulse Response (IIR) Filter, Radix-2 Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT), Radix-2 Discrete Cosign Transform (DCT)/Inverse Discrete Cosign Transform (IDCT), Golay Correlator, Local Oscillator/Mixer.

Claims

1. A reconfigurable arithmetic node (RAN) in an adaptive computing system configurable to execute any one of a plurality of target algorithms, wherein the target algorithms include an Asymmetric FIR filter, a Symmetric FIR Filter, a Complex Multiply FIR Filter, a Sum-of-absolute-differences, a Bi-linear interpolation, a Bi-quad IIR filter, a Radix-2 Fast Fourier Transform/Inverse Fast Fourier Transform, a Radix -2 Discrete Cosine Transform/Inverse Discrete Cosign Transform, a Golay Correlator, and a Local Oscillator/Mixer, the RAN comprising an execution unit having:

a program control unit (PCU) for controlling task set-up and tear down in the RAN for execution of the one target algorithm;

an algorithm control unit (ACU) for controlling a data path unit and generating a control sequence associated with the one target algorithm of the plurality of algorithms and an address generator unit to selected and enable execution of the one target algorithm; and

a finite state machine for receiving control signals to execute one of the target algorithms and for selecting between the PCU and the ACU to execute the one target algorithm.

2. A node as claimed in claim 1 wherein the address generator unit provides addresses to support execution of the algorithm, including two read addresses and one write address to a memory system and two to read address.

3. A node as claimed in claim 2 wherein the address generator unit includes a common part used for substantially all of the target algorithms and an algorithm specific part that supports execution of the specific target algorithm.

4. A node as claimed in claim 1, wherein the address generator unit including first Fourier Transform generator, powers of two delay generators for Golay Correlators and a row/column counter for two dimension discrete cosine transform generation.

5. A node as claimed in claim 4, wherein the address generation unit includes two read address generators and a write address generator.

6. A node as claimed in claim 5 wherein one of the read generator units include Fast Fourier Transform (FFT) addressing, power of two delay generation for a Golay Correlator, and forward-background indexing to support computation of symmetric Finite Impulse Response (FIR) filter outputs.

7. A node as claimed in claim 6, wherein one of the read generators is configured to support a local oscillator and Fast Fourier Transform (FFT) table address generation.

8. A node as claimed in claim 2, further comprising a data path unit coupled to the address generator unit, the algorithm control unit and the control program unit and configured to implement trig tables, symmetric filters and motion information calculations as the target algorithms.

9. A node as claimed in claim 1, wherein the data path unit comprises first and second arithmetic logic units (ALU), a multiplier, an adder/xnor unit, first and second register files, and a pipeline register interconnected by a plurality of multiplexers and between first and second memories and an output, to provide execution of the target algorithms.

10. An adaptive computer comprising a plurality of reconfigurable arithmetic nodes coupled together by a matrix interconnection network for transferring data control and configuration information between and among the reconfigurable arithmetic nodes, each of the nodes comprising a reconfigurable arithmetic node (RAN) configurable to execute any one of a plurality of target algorithms, wherein the target algorithm include an Asymmetric FIR filter, a Symmetric FIR Filter, a Complex Multiply FIR Filter, a Sum-of-absolute-differences, a Bi-linear interpolation, a Bi-quad IIR filter, a Radix-2 Fast Fourier Transform/Inverse Fast Fourier Transform, a Radix -2 Discrete Cosine Transform/Inverse Discrete Cosine Transform, a Golay Correlator, and a Local Oscillator/Mixer, the RAN comprising an execution unit having:

a program control unit (PCU) for controlling task set-up and tear down in the RAN for execution of the one target algorithm;

an algorithm control unit (ACU) for controlling a data path unit and generating a control sequence associated with the one targeted algorithm of the plurality of target algorithms and an address generator unit to enable execution of a specific one of the target algorithms; and

a finite state machine for receiving control signals to execute one of the target algorithms and for selecting between the PCU and the ACU to execute the one target algorithm.

11. A node as claimed in claim 10 wherein the address generator unit provides addresses to support execution of the algorithm, including two read addresses and one write address to a memory system.

12. A node as claimed in claim 10 wherein the address generator unit includes a common part used for substantially all of the target algorithms and an algorithm specific part that supports execution of the specific target algorithm.

13. A node as claimed in claim 12, wherein the address generator unit including first Fourier Transform generator, powers of two delay generators for a Golay Correlator and a row/column counter for two dimension discrete cosine transform generation.

14. A node as claimed in claim 13, wherein the address generation unit includes two read address generators and a write address generator.

15. A node as claimed in claim 14 wherein one of the read address generator units include Fast Fourier Transform (FFT) addressing, power of two delay generation for a Golay Correlator, and forward-background indexing to support computation of symmetric Finite Impulse Response (FIR) filter outputs.

16. A node as claimed in claim 15, wherein one of the read generators is configured to support a local oscillator and Fast Fourier Transform (FFT) table address generation.

17. A node as claimed in claim 11, further comprising a data path unit coupled to the address generator unit, the algorithm control unit and the control program unit and configured to implement trig tables, symmetric filters and motion information calculations as the target algorithms.

18. A node as claimed in claim 10, wherein the data path unit comprises first and second arithmetic logic units (ALU), a multiplier, an address unit, first and second register files, and a pipeline register interconnected by a plurality of multiplexers and between first and second memories and an output, to provide execution of the target algorithms.