Vehicle computer system with audio entertainment system

• US 7,433,974 B2
• Filed: 05/18/2005
• Issued: 10/07/2008
• Est. Priority Date: 01/07/1998
• Status: Expired due to Fees

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Li, Hang, Moeller, Mark M., Beckert, Richard D.
• Primary Examiner(s): Hafiz; Tariq
• Assistant Examiner(s): SUN, SCOTT C
• Application Number:
  US11/132,070
• Publication Number:
  US 20050209719A1
• Time in Patent Office: 1,238 Days
• Field of Search: 710/20, 710/22
• US Class Current: 710/20
• CPC Class Codes: B60R 16/0315 using multiplexing techniques multiplexing for transmission of signals G08C15/00; multiplexing for electrical communication in general H04J
• CPC Class Codes: B60R 2016/0322 Temporary code for documents to be reclassified to G08C, H04L or H04Q

Abstract

A vehicle computer system has an audio entertainment system implemented in a logic unit and audio digital signal processor (DSP) independent from the host CPU. The audio entertainment system employs a set of ping/pong buffers and direct memory access (DMA) circuits to transfer data between different audio devices. Audio data is exchanged using a mapping overlay technique, in which the DMA circuits for two audio devices read and write to the same memory buffer. The computer system provides an audio manager API (application program interface) to enable applications running on the computer to control the various audio sources without knowing the hardware and implementation details of the underlying sound system. Different audio devices and their drivers control different functionality of the audio system, such as equalization, volume controls and surround sound decoding. The audio manager API transfers calls made by the applications to the appropriate device driver(s). The computer system also supports a speech recognition system. Speech utterances are picked up by a microphone and sampled at an internal sampling rate. However, the speech recognition system employs a lower sampling rate. The computer system converts microphone data from the higher internal sampling rate to the desired sampling rate by piggybacking the microphone data on command/message streams to an SPI (serial peripheral interface) of the audio DSP. The DSP performs normal low-pass filtering and down sampling on the data stream and then uses the SPI to send out the microphone data at the lower sampling rate.

Claims

1. An entertainment system for a vehicle comprising:

a housing of a size suitable to be mounted in a vehicle dashboard;

a faceplate module residing on a faceplate attached to the housing;

a computer module having a first processor configured to execute one or more applications; and

a support module mounted within the housing, the support module being coupled to the computer module and the faceplate module via a communications bus, the support module including;

a data memory including one or more ping/pong buffers;

a data processor to process audio data; and

a logic unit configured to receive audio data from one or more peripheral audio sources, the logic unit including one or more audio source direct memory access (DMA) circuits, with each audio source DMA circuit being associated with a specific peripheral audio source, and a data processor DMA circuit associated with the data processor,

wherein each audio source DMA circuit is configured to;

write audio data received from a peripheral audio source to which the audio source DMA circuit is associated to a storage area within the data memory, while the data processor DMA circuit reads previously written audio data from the storage area within the data memory;

and further wherein the data processor DMA circuit is configured to;

transmit the previously written audio data to the data processor.

2. An entertainment system for a vehicle as recited in claim 1, further comprising a synchronization circuit to synchronize a first rate at which a first audio source DMA circuit writes the audio data into the data memory with a second rate at which the data processor DMA circuit reads the previously written audio data from the data memory.

3. An entertainment system for a vehicle as recited in claim 1, wherein the logic unit concurrently transfers audio data from multiple different audio sources to the data processor for concurrent processing.

4. An entertainment system for a vehicle as recited in claim 1, wherein the one or more audio source direct memory access (DMA) circuits are configured to write audio data to a ping buffer in the storage area while the data processor DMA circuit reads previously written audio data from a pong buffer in the storage area.

5. An entertainment system for a vehicle as recited in claim 4, further comprising a master clock adjuster circuit configured to monitor a first rate at which the audio data is written to the ping buffer and adjust a reference audio clock associated with the data processor DMA circuit reading the previously written audio data from the pong buffer at a second rate such that the first rate is equal to the second rate.

6. An entertainment system for a vehicle as recited in claim 1, wherein the one or more peripheral audio sources include one or more of:

a security system;

a navigation system;

a CD-ROM changer;

a television tuner.

7. An entertainment system for a vehicle as recited in claim 1, wherein the communications bus coupling the faceplate module and the support module includes a high speed serial interface, and further wherein the communications bus coupling the support module to the computer module includes a multi-bit bus.

8. An entertainment system for a vehicle as recited in claim 1, wherein the logic unit is further configured to establish a master audio clock signal for use throughout the entertainment system.

9. A vehicle computer system comprising:

a housing having a base unit and a faceplate;

a first processor mounted to the faceplate to form a faceplate module;

a computer module having a second processor; and

a support module mounted to the base unit, the support module being coupled to the computer module and the faceplate module via a communications bus, the support module including;

an AM/FM tuner module

a data memory including one or more ping/pong buffers;

a digital signal processor; and

a logic unit configured to receive audio data from the AM/FM tuner module and one or more peripheral audio sources, the logic unit including an audio source DMA circuit associated with the AM/FM tuner module and one or more other audio source DMA circuits associated with specific ones of the one or more peripheral audio sources, and further wherein the logic unit includes at least one data processor DMA circuit associated with the digital signal processor,

wherein each audio source DMA circuit is configured to;

write audio data to a ping buffer within the data memory, while the at least one data processor DMA circuit reads audio data from a pong buffer within the data memory.