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Secure verification using a set-top-box chip

  • US 7,434,065 B2
  • Filed: 11/06/2003
  • Issued: 10/07/2008
  • Est. Priority Date: 09/29/2003
  • Status: Expired due to Fees
First Claim
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1. A set-top-box chip in a set-top-box comprising:

  • a first linear feedback shift register;

    a first circuitry for generating a first hashed data sequence from a verification sequence transmitted by a head-end;

    a second circuitry for implementing a hashing function for generating a second hashed data sequence;

    a third circuitry for generating an encryption key which is a function of an output generated by said first linear feedback shift register;

    a one time programmable memory for storing a key, a word, and an identifier word;

    a non-volatile memory for storing said output of said first linear feedback shift register, a timer value, and an enable status indicator;

    a fourth circuitry for synchronizing said first linear feedback shift register to a second linear feedback shift register in said head-end; and

    a fifth circuitry for comparing said first hashed data sequence with said second hashed data sequence, said fifth circuitry generating a control signal for incrementing the state of said first linear feedback shift register enabling operation of said set-top-box chip if said first hashed data sequence is equal to said second hashed data sequence.

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