System and method for read synchronization of memory modules

• US 7,434,081 B2
• Filed: 05/10/2006
• Issued: 10/07/2008
• Est. Priority Date: 12/29/2003
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M., LaBerge, Paul
• Primary Examiner(s): Perveen; Rehana
• Assistant Examiner(s): Brown; Michael J
• Application Number:
  US11/432,060
• Publication Number:
  US 20060206679A1
• Time in Patent Office: 881 Days
• Field of Search: 713/500
• US Class Current: 713/500
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234

Abstract

A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.

Claims

1. A memory read synchronization system, comprising:

a first memory component configured to provide read data and a first read signal responsive to an internal memory request;

a second memory component configured to store the read data responsive to the first read signal and to output the stored read data responsive to a second read signal;

a memory controller component being operable to issue the internal memory request to the first memory component in response to an external memory request while adjusting the timing of the internal memory request responsive to a timing adjust signal;

a timing comparison component operable to compare timing between the first read signal and the second read signal and to generate the timing adjust signal corresponding to the compared timing.

2. The memory read synchronization system of claim 1 wherein the memory controller component is operable to increase a period between receiving the external memory request and generating the internal memory request responsive to the timing adjust signal that is indicative of a decrease in the timing between storing the read data in the second memory component and outputting the stored read data from the second memory component, the memory sequencer further being operable to decrease a period between receiving the external memory request and generating the internal memory request responsive to the timing adjust signal that is indicative of an increase in the timing between storing the read data in the second memory component and outputting the stored read data from the second memory component.

3. The memory read synchronization system of claim 1 wherein the timing comparison component comprises:

a first counter operable to increment in response to the read data being stored in the second memory component;

a second counter operable to increment in response to the stored read data being output from the second memory component; and

a comparator component operable to compare the first counter to the second counter and to generate the timing adjust signal corresponding to the compared timing.

4. The memory read synchronization system of claim 1 wherein the second read signal is the core clock signal.

5. A memory read synchronization circuit comprising:

at least one memory device operable to output read data signals and a buffer write signal responsive to a read request;

a buffer configured to receive the read data signals being clocked into the buffer responsive to the buffer write signal, the buffer further configured to output the read data signals responsive to a buffer read signal;

a memory sequencer coupled to the at least one memory device and the buffer, and operable to generate the read request responsive to an external memory request while adjusting the timing of the generated read request responsive to a timing adjust signal; and

a comparator coupled to the memory sequencer and operable to compare the timing between the buffer read signal and the buffer write signal and generate the timing adjust signal corresponding to the compared timing.

6. The memory read synchronization circuit of claim 5 wherein the memory sequencer is operable to increase a period between receiving the external memory request and generating the read request responsive to the timing adjust signal that is indicative of a decrease in the timing between clocking the read data signals into the buffer and outputting the read data signals from the buffer, the memory sequencer further being operable to decrease a period between receiving the external memory request and generating the read request responsive to the timing adjust signal that is indicative of an increase in the timing between clocking the read data signals into the buffer and outputting the read data signals from the buffer.

7. The memory read synchronization circuit of claim 5 wherein the memory read synchronization circuit further comprises:

a first counter coupled to the comparator and operable to increment in response to the read data signals being clocked into the buffer;

a second counter coupled to the comparator and operable to increment in response to outputting the read data signals from the buffer; and

wherein the comparator is operable to compare the first counter to the second counter and to generate the timing adjust signal corresponding to the compared timing.

8. The memory read synchronization circuit of claim 5 wherein the buffer read signal is the core clock signal.

9. A method of reading data from a memory module, comprising:

receiving memory requests for access to a memory device in the memory module;

coupling the memory requests to the memory device responsive to the received memory request, at least some of the memory requests being memory requests to read data;

receiving read data responsive to the read memory requests;

writing the read data to a buffer;

outputting the read data from the buffer;

incrementing a write pointer in response to storing the read data in the buffer;

incrementing a read pointer in response to outputting the read data from the buffer;

comparing the timing between writing the read data to the buffer and outputting the read data from the buffer by comparing the write pointer to the read pointer; and

adjusting the timing at which read memory requests are coupled to the memory device as a function of the compared timing.

10. The method of claim 9 wherein the act of receiving memory requests for access to the memory device in the memory module comprises receiving optical signals corresponding to the memory requests.

11. The method of claim 9 wherein the buffer comprises a circular buffer.