Non-volatile memory system having a pseudo pass function

• US 7,434,111 B2
• Filed: 04/04/2005
• Issued: 10/07/2008
• Est. Priority Date: 11/05/2004
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanaka, Tatsuya, Inoue, Atsushi, Sugiura, Yoshihisa
• Primary Examiner(s): Ellis; Kevin
• Assistant Examiner(s): OTTO, ALAN
• Application Number:
  US11/097,188
• Publication Number:
  US 20060117214A1
• Time in Patent Office: 1,282 Days
• Field of Search: 714/5, 714/48, 714/704, 714/705, 711/102, 711/103, 365/185.09, 365/200
• US Class Current: 714/48
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/832 with disconnection of faulty elements

Abstract

A non-volatile memory system comprises a non-volatile memory and a memory controller controlling the non-volatile memory. The non-volatile memory has a pseudo pass function of returning a pass as a status even if a bit error reaching allowable number of bits occurs after at least one of a write or erase sequence is completed. The memory controller has an allowable bit change function of changing the upper limit value of the allowable number of bits.

Claims

1. A non-volatile memory system comprising:

a non-volatile memory; and

a memory controller controlling the non-volatile memory, the non-volatile memory having a pseudo pass function of returning a pass as a status even if bit error reaching an allowable number of bits occurs after at least one of a write or erase sequence is completed, the memory controller having an allowable bit changing function of changing an upper limit value of the allowable number of bits within a range of a number of bits correctable by a checking/correcting function, the non-volatile memory having a rewritable allowable bit storage section storing the upper limit value of the allowable number of bits.

2. The system according to claim 1, wherein the upper limit value of the allowable number of bits is changed based on a number of bit errors allowed as a pseudo pass.

3. The system according to claim 2, wherein the non-volatile memory includes:

a status storage section storing a status and a number of bit errors allowed as the pseudo pass in a stares read, wherein the memory controller includes;

an allowable bit change processing section reading the status and the number of bit errors allowed as the pseudo pass, comparing the number of bit errors allowed as the pseudo pass with a number of bits correctable by error checking/correcting function, and based on the comparison result, changing the upper limit value of the allowable number of bits within a range of the number of correctable bits, and writing the changed upper limit value of the allowable number of bits in the allowable bit storage section.

4. The system according to claim 1, wherein the upper limit value of the allowable number of bits is changed based on a number of rewrite times of the non-volatile memory.

5. The system according to claim 4, wherein the memory controller includes:

a count section counting a number of rewrite times of the non-volatile memory; and

an allowable bit change processing section changing the upper limit value of the allowable number of bits within a range of the number of correctable bits based on the count result, and writing the changed upper limit value of the allowable number of bits in the allowable bit storage section.

6. The system according to claim 3, wherein the rewritable storage section is provided outside a memory cell array of the non-volatile memory.

7. The system according to claim 4, wherein the rewritable storage section is provided outside a memory cell array of the non-volatile memory.

8. The system according to claim 5, wherein the rewritable storage section is provided outside a memory cell array of the non-volatile memory.

9. The system according to claim 3, wherein the rewritable storage section is provided in a memory cell array of the non-volatile memory.

10. The system according to claim 4, wherein the rewritable storage section is provided outside in a memory cell array of the non-volatile memory.

11. The system according to claim 5, wherein the rewritable storage section is provided in a memory cell array of the non-volatile memory.

12. The system according to claim 9, wherein the rewritable storage section exists in a redundancy page of the memory cell array, and the redundancy page exists outside a data area of one page.

13. The system according to claim 10, wherein the rewritable storage section exists in a redundancy page of the memory cell array, and the redundancy page exists outside a data area of one page.

14. The system according to claim 11, wherein the rewritable storage section exists in a redundancy page of the memory cell array, and the redundancy page exists outside a data area of one page.

15. The system according to claim 12, wherein the allowable number of bits is shown by any of the number of data “

0”

or “

1”

of the allowable bit storage section.

16. The system according to claim 13, wherein the allowable number of bits is shown by any of the number of data “

0”

or “

1”

of the allowable bit storage section.

17. The system according to claim 14, wherein the allowable number of bits is shown by any of the number of data “

0”

or “

1”

of the allowable bit storage section.

18. The system according to claim 1, wherein the upper limit value of the allowable number of bits is changed every block of the non-volatile memory.

19. The system according to claim 1, wherein the upper limit value of the allowable number of bits is changed every page of the non-volatile memory.

20. The system according to claim 1, wherein the non-volatile memory is a multi-value memory.