Methods, circuits, architectures, software and systems for determining a data transmission error and/or checking or confirming such error determinations
First Claim
1. A method of determining or confirming an error in transmitted data, comprising the steps of:
- a) receiving said transmitted data and then partitioning said received data into at least one data line and a last line, each of said at least one data line and said last line having a first fixed length, and the last line containing appended error checking code calculated on said transmitted data;
b) when said partitioned received data has a remainder, said remainder having any length less than said first fixed length and greater than zero, appending a pad vector to said remainder, the pad vector having a length sufficient to form a first data line with said first fixed length when the pad vector is appended to said remainder;
c) performing an error checking calculation on said first line, said at least one data line and any data in said last line to generate an error checking vector;
d) iterating the error checking calculation on said appended error checking code using said error checking vector to provide a calculated error checking result;
e) determining a state of said calculated error checking result; and
f) if said calculated error checking result has a predetermined state, indicating that there is no error in said transmitted data.
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Accused Products
Abstract
Methods, circuits, architectures, and systems for error detection in transmitted data. The method generally includes the steps of (a) performing an error checking calculation on the transmitted data and appended error checking code; (b) determining the calculated error checking code state; and (c) if it has a predetermined state, indicating that there is no error in the transmitted data. The circuitry generally comprises (1) an error checking code calculation circuit configured to calculate error checking code on the transmitted data and the appended error checking code; (2) a vector selector configured to select one of a plurality of error checking vectors; and (3) a logic circuit configured to determine the calculated error checking code state and, if it has a predetermined state, indicate that there is no error in the transmitted data. The software generally includes a set of instructions configured to implement or carry out the present method. The architectures and/or systems generally include those that embody one or more of the inventive concepts disclosed herein. In the present invention, an error checking calculation is performed on error checking code transmitted with the data. If the transmitted data and error checking code are error-free, the error checking calculation gives a result having a known and/or predetermined state. This technique enables one to confirm or determine that the data transmission was error-free without use of or need for a wide, complicated comparator, thereby reducing the chip area dedicated to error detection, increasing the utilization efficiency of the circuitry on the chip, and reducing power consumption.
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Citations
68 Claims
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1. A method of determining or confirming an error in transmitted data, comprising the steps of:
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a) receiving said transmitted data and then partitioning said received data into at least one data line and a last line, each of said at least one data line and said last line having a first fixed length, and the last line containing appended error checking code calculated on said transmitted data; b) when said partitioned received data has a remainder, said remainder having any length less than said first fixed length and greater than zero, appending a pad vector to said remainder, the pad vector having a length sufficient to form a first data line with said first fixed length when the pad vector is appended to said remainder; c) performing an error checking calculation on said first line, said at least one data line and any data in said last line to generate an error checking vector; d) iterating the error checking calculation on said appended error checking code using said error checking vector to provide a calculated error checking result; e) determining a state of said calculated error checking result; and f) if said calculated error checking result has a predetermined state, indicating that there is no error in said transmitted data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A circuit for determining a data transmission error and/or checking a data transmission error determination, comprising:
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a) a data partitioning circuit configured to receive transmitted data and an appended error checking code calculated on said transmitted data, and then partition said transmitted data and said appended error checking code into at least one data line having a first fixed length and a last line comprising said appended error checking code and having said first fixed length; b) an error checking code calculation circuit configured to perform error checking calculations on a first data line, said at least one data line and any data in said last line to generate an error checking vector, and iterate the error checking calculation on said appended error checking code using said error checking vector to provide a calculated error checking result; c) a vector selector configured to insert a pad vector to said first data line when said partitioned transmitted data and appended error checking code comprises a remainder, said remainder having any length less than said first fixed length and greater than zero, and select one of a plurality of error checking vectors, said plurality of error checking vectors comprising an initial vector and an error checking code feedback vector, the pad vector having a length providing said first data line with said first fixed length when appended to said remainder; and d) a logic circuit configured to determine a state of said calculated error checking result and, if said calculated error checking result has a predetermined state, indicate that there is no error in said transmitted data. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. A circuit for determining a data transmission error and/or confirming an error determination, comprising:
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a) means for receiving and then partitioning said transmitted data and said appended error checking code into (i) at least one data line having a first fixed length, and (ii) a last line comprising said appended error checking code and having said first fixed length; b) means for performing error checking calculations on a first data line, said at least one data line and any data in said last line to generate an error checking vector, and iterating the error checking calculation on said appended error checking code using said error checking vector to provide a calculated error checking result; c) means for selecting one of a plurality of error checking vectors, said plurality of error checking vectors comprising an initial vector, an error checking code feedback vector, and a pad vector; d) means of inserting said pad vector to said first data line when said partitioned transmitted data and said appended error checking code comprises a remainder, said remainder having any length less than said first fixed length and greater than zero, said pad vector having a length providing said first data line with said first fixed length when appended to said remainder; and e) means for determining a state of said calculated error checking result and, if said calculated error checking result has a predetermined state, indicating that there is no error in said transmitted data. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68)
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Specification