Active matrix type organic light emitting diode device and fabrication method thereof

• US 7,435,630 B2
• Filed: 10/27/2005
• Issued: 10/14/2008
• Est. Priority Date: 10/29/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lee, Kyung-Eon
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US11/258,956
• Publication Number:
  US 20060091399A1
• Time in Patent Office: 1,083 Days
• Field of Search: 257/59, 257/71, 257/72, 257/75, 257290-292, 257/443, 257/444, 257E27131-E27133, 438/48, 438/66, 438/67, 438/73, 438/80, 438/82, 438/99, 438/128, 438/149, 438/151
• US Class Current: 438/149
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H10K 50/86 Arrangements for improving contrast, e.g. preventing reflection of ambient light
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/8791 Arrangements for improving contrast, e.g. preventing reflection of ambient light

Abstract

An active matrix type organic light emitting diode (AMOLED) device and its fabrication method are discussed. In one embodiment, an OLED device includes an EL configured to emit light, a driving TFT configured to control the EL, a storage capacitor coupled to the driving TFT, and at least one insulation layer configured to insulate at least one of the EL, the driving TFT and the storage capacitor, and including a plurality of recesses formed on a surface of the at least one insulation layer.

Claims

1. A method for fabricating an active matrix type organic light emitting diode (AMOLED) device, the method comprising:

forming a buffer layer on an insulation substrate;

forming a semiconductor layer on the buffer layer;

forming a gate insulation film on the semiconductor layer;

forming a gate electrode and a capacitor lower electrode on the gate insulation film and forming a drain electrode region and a source electrode region at the semiconductor layer below both sides of the gate electrode;

forming a first interlayer insulation film on a surface of the resulting structure;

forming a cathode electrode and a capacitor upper electrode on the first interlayer insulation film;

forming a second interlayer insulation film on a surface of the resulting structure;

forming a plurality of contact holes exposing portions of the cathode electrode, the drain electrode region, the source electrode region, the capacitor upper electrode and the capacitor lower electrode through at least one etching process;

forming a first conductive layer pattern connecting the cathode electrode and the drain electrode region, and a second conductive layer pattern connecting the source electrode region and the capacitor upper electrode through the plurality of contact holes;

forming a passivation film on a surface of the resulting structure and patterning the passivation film to form an opening exposing a portion of the cathode electrode;

forming an EL layer inside the opening and forming an anode electrode thereon; and

forming a plurality of recesses on a surface of at least one of the buffer layer, the gate insulation layer, the first interlayer insulation film, the second interlayer insulation film and the passivation film, wherein the plurality of recesses are formed such that they are not located at the same correspondence positions of overlapped upper and lower layers.

2. The method of claim 1, wherein the plurality of recesses are irregularly patterned.

3. The method of claim 1, wherein the plurality of recesses are formed on surfaces of the buffer layer, the gate insulation film, the first interlayer insulation film, the second interlayer insulation film and the passivation layer.

4. The method of claim 1, wherein the plurality of recesses have a different size.

5. The method of claim 1, wherein a ratio of the size of an area where the plurality of recesses are formed and the size of an area where no recess is formed is about 1:

1.

6. The method of claim 1, wherein, in the step of forming the plurality of recesses, the recesses are formed by using a mask or through a double exposure process.

7. A method of forming an organic light emitting diode (OLED) device, the method comprising:

forming an EL configured to emit light;

forming a driving TFT configured to control the EL;

forming a storage capacitor coupled to the driving TFT; and

forming at least one insulation layer configured to insulate at least one of the EL, the driving TFT and the storage capacitor, wherein the at least one insulation layer includes a plurality of recesses formed on a surface of the at least one insulation layer, wherein in the step of forming the at least one insulation layer, the at least one insulation layer involves a plurality of different insulation layers, each of the insulation layers including a plurality of recesses on a surface of the corresponding insulation layer.

8. The method of claim 7, wherein in the step of forming the at least one insulation layer, the plurality of recesses have irregular shapes and/or sizes.

9. The method of claim 7, wherein in the step of forming the at least one insulation layer, the at least one insulation layer includes at least one of the following:

a buffer layer on which the EL, the driving TFT and the storage capacitor are formed;

a gate insulation layer between source/drain electrode regions and a gate electrode of the driving TFT;

a first interlayer insulation film on the gate electrode of the driving TFT;

a second interlayer insulation film on the storage capacitor, or

a passivation film on an electrode of the EL.

10. The method of claim 7, wherein in the step of forming the at least one insulation layer, a ratio of a size of a total area on the at least one insulation layer where the plurality of recesses are formed and a size of a total area on the at least one insulation layer where no recess is formed is about 1:

1.