Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel

• US 7,435,988 B2
• Filed: 01/25/2005
• Issued: 10/14/2008
• Est. Priority Date: 06/26/2003
• Status: Expired due to Term

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Hytha, Marek, Mears, Robert J., Yiptong, Jean Augustin Chan Sow Fook, Kreps, Scott A., Dukovski, Ilija
• Primary Examiner(s): Pham; Long
• Application Number:
  US11/042,270
• Publication Number:
  US 20050173697A1
• Time in Patent Office: 1,358 Days
• Field of Search: 257/28, 257/20, 257/288
• US Class Current: 257/28
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor device may include a substrate and at least one MOSFET adjacent the substrate including a superlattice. The superlattice may include a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers. Each group of layers of the superlattice may comprise a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The MOSFET may further include source, drain, and gate regions defining a channel through at least a portion of the semiconductor cap layer.

Claims

1. A semiconductor device comprising:

a substrate; and

at least one MOSFET adjacent said substrate and comprising

a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers,

each group of layers of said superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween, the non-semiconductor selected from the group consisting of at least one of oxygen, nitrogen, fluorine, and carbon, and

source, drain and gate regions defining a channel through at least a portion of said semiconductor cap layer.

2. The semiconductor device of claim 1 wherein the channel lies entirely within said semiconductor cap layer.

3. The semiconductor device of claim 1 wherein said semiconductor cap layer comprises the same semiconductor as each base semiconductor portion.

4. The semiconductor device of claim 1 wherein said semiconductor cap layer comprises a different semiconductor than each base semiconductor portion.

5. The semiconductor device of claim 1 wherein said semiconductor cap layer has a thickness of greater than about 10 Angstroms.

6. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

7. The semiconductor device of claim 1 wherein each non-semiconductor monolayer consists of oxygen.

8. The semiconductor device of claim 1 wherein each non-semiconductor layer is a single monolayer thick.

9. The semiconductor device of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.

10. The semiconductor device of claim 1 wherein said gate region comprises a gate electrode layer and a gate dielectric layer between said gate electrode layer and said semiconductor cap layer.

11. The semiconductor device of claim 1 wherein all of said base semiconductor portions are a same number of monolayers thick.

12. The semiconductor device of claim 1 wherein at least some of said base semiconductor portions are a different number of monolayers thick.

13. The semiconductor device of claim 1 wherein all of said base semiconductor portions are a different number of monolayers thick.

14. The semiconductor device of claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VT semiconductors.

15. The semiconductor device of claim 1 wherein said superlattice further comprises at least one type of conductivity dopant therein.

16. A semiconductor device comprising:

a substrate; and

at least one MOSFET adjacent said substrate and comprising

a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers,

each group of layers of said superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween, the non-semiconductor selected from the group consisting of at least one of oxygen, nitrogen, fluorine, and carbon,

said semiconductor cap layer comprising the same semiconductor as each base semiconductor portion, and

source, drain and gate regions defining a channel lying entirely within said semiconductor cap layer.

17. The semiconductor device of claim 16 wherein said semiconductor cap layer has a thickness of greater than about 10 Angstroms.

18. The semiconductor device of claim 16 wherein each base semiconductor portion comprises silicon.

19. The semiconductor device of claim 16 wherein each non-semiconductor monolayer consists of oxygen.

20. The semiconductor device of claim 16 wherein each non-semiconductor layer is a single monolayer thick.

21. The semiconductor device of claim 16 wherein each base semiconductor portion is less than eight monolayers thick.

22. The semiconductor device of claim 16 wherein said gate region comprises a gate electrode layer and a gate dielectric layer between said gate electrode layer and said semiconductor cap layer.

23. The semiconductor device of claim 16 wherein all of said base semiconductor portions are a same number of monolayers thick.

24. The semiconductor device of claim 16 wherein at least some of said base semiconductor portions are a different number of monolayers thick.

25. The semiconductor device of claim 16 wherein all of said base semiconductor portions are a different number of monolayers thick.

26. The semiconductor device of claim 16 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VT semiconductors.

27. A semiconductor device comprising:

a substrate; and

at least one MOSFET adjacent said substrate and comprising

a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers,

each group of layers of said superlattice comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together with the chemical bonds traversing the at least one oxygen monolayer therebetween, and

source, drain and gate regions defining a channel through at least a portion of said semiconductor cap layer.

28. The semiconductor device of claim 27 wherein the channel lies entirely within said semiconductor cap layer.

29. The semiconductor device of claim 27 wherein said semiconductor cap layer comprises the same semiconductor as each base silicon portion.

30. The semiconductor device of claim 27 wherein said semiconductor cap layer comprises a different semiconductor than each base silicon portion.

31. The semiconductor device of claim 27 wherein said semiconductor cap layer has a thickness of greater than about 10 Angstroms.

32. The semiconductor device of claim 27 wherein each at least one oxygen monolayer is a single monolayer thick.

33. The semiconductor device of claim 27 wherein each base silicon portion is less than eight monolayers thick.

34. The semiconductor device of claim 27 wherein said gate region comprises a gate electrode layer and a gate dielectric layer between said gate electrode layer and said semiconductor cap layer.

35. The semiconductor device of claim 27 wherein all of said base silicon portions are a same number of monolayers thick.

36. The semiconductor device of claim 27 wherein at least some of said base silicon portions are a different number of monolayers thick.

37. The semiconductor device of claim 27 wherein all of said base silicon portions are a different number of monolayers thick.