Dense trench MOSFET with decreased etch sensitivity to deposition and etch processing

• US 7,436,021 B2
• Filed: 07/11/2003
• Issued: 10/14/2008
• Est. Priority Date: 11/20/2001
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Dolny, Gary M., Hao, Jifa, Ridley, Rodney S.
• Primary Examiner(s): BRYANT, KIESHA ROSE
• Application Number:
  US10/618,067
• Publication Number:
  US 20040104427A1
• Time in Patent Office: 1,922 Days
• Field of Search: 257/328, 257/329, 257/330, 257/335, 438/270
• US Class Current: 257/328
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET 100 has a source metal 112 that contacts silicided source regions 114 through vias 160 etched in an insulating layer 200. The silicide layer 225 provides for a relatively small but highly conductive contact and thus reduces RDSON. The insulating material may be any suitable material including and not limited to one or a combination of materials such as BPSG, PSG, silicon dioxide and silicon nitride. The insulating layer is relatively thin and does not extend deeply into the gate trench.

Claims

1. A power semiconductor device with trench gates comprising:

a) a semiconductor substrate;

b) a source layer on one surface of said substrate and comprising a high concentration of a dopant of a first polarity;

c) a single drain region on the other surface of said substrate;

d) a well layer beneath said source layer doped with a dopant of a second polarity opposite to said first polarity;

e) a region lightly doped with said one polarity positioned above said drain region and below said well layer;

f) plurality of trenches penetrating said source layer and terminating in said region lightly doped with said one polarity, said trenches substantially filled with conductive material;

g) a highly conductive layer on the surface of said source layer comprising a material reacted from a metal and said substrate which forms a highly conductive path extending from a first of said plurality of trenches to a of said plurality of trenches;

h) an insulating layer on said highly conductive layer and on said conductive material in said trenches;

i) vias formed in said insulating layer and extending to said highly conductive layer; and

j) conductive material filling said vias for contacting said highly conductive layer.

2. The power semiconductor device of claim 1 wherein said trenches are filled with polysilicon and the top surface of said polysilicon is covered with a highly conductive material reacted from a metal and said polysilicon.

3. The power semiconductor device of claim 1 wherein said highly conductive layer is a silicide.

4. The power semiconductor device of claim 3 wherein said silicide is reacted from platinum or titanium.

5. The power semiconductor device of claim 1 wherein said insulating material on said highly conductive layer is BPSG, PSG, silicon dioxide or silicon nitride.

6. The power semiconductor device of claim 1 wherein said trenches are lined with a trench wall insulating material and said insulating material on said highly conductive layer contacts the ends of said trench wall insulating layers lining said walls of said trenches.

7. The power semiconductor device of claim 1 wherein one or more vias terminated on said surface of said highly conductive layer make electrical contact between said highly conductive source layer and conductive material filling said vias.