Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout

• US 7,436,022 B2
• Filed: 04/29/2006
• Issued: 10/14/2008
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Ng, Daniel, Lui, Sik K
• Primary Examiner(s): Tran; Thien F
• Application Number:
  US11/413,249
• Publication Number:
  US 20060202264A1
• Time in Patent Office: 899 Days
• Field of Search: 257/260, 257328-330, 257/490, 257/495, 257/563, 257/564, 438/212, 438/268, 438/560
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells and a junction barrier Schottky (JBS) area. The semiconductor power device includes the JBS area that further includes a plurality of Schottky diodes each having a PN junction disposed on an epitaxial layer near a top surface of a semiconductor substrate wherein the PN junction further includes a counter dopant region disposed in the epitaxial layer for reducing a sudden reversal of dopant profile near the PN junction for preventing an early breakdown in the PN junction.

Claims

1. A semiconductor power device comprising an active cell area having a plurality of power transistor cells and a Junction Barrier controlled Schottky (JBS) area wherein:

said JBS area comprising a plurality of Schottky diodes interspersed between a plurality of PN junctions disposed on an epitaxial layer near a top surface of a semiconductor substrate wherein said JBS area further includes a counter dopant region disposed in said epitaxial layer for reducing a sudden reversal of dopant profile near said PN junction for preventing an early breakdown in said PN junction.

2. The semiconductor power device of claim 1 wherein:

said JBS comprising body-type-dopant regions disposed in an epitaxial layer wherein said counter dopant region comprises a reduced epitaxial dopant region.

3. The semiconductor power device of claim 1 wherein:

said JBS comprising P-type-dopant regions disposed in a N-type-dopant epitaxial layer wherein said counter dopant region comprises a reduced N-type dopant region surrounding said P-type-dopant regions for reducing said sudden reversal of dopant profile near said PN junction.

4. The semiconductor power device of claim 1 wherein:

said semiconductor power device further comprising a metal oxide semiconductor field effect transistor (MOSFET) device.

5. The semiconductor power device of claim 1 further comprising:

a macro cell structure wherein each macro cell comprises a plurality of MOSFET cells and a JBS area.

6. The semiconductor power device of claim 1 wherein:

said epitaxial layer further comprising an upper epitaxial layer having a reduced dopant concentration near a top surface encompassing said Schottky diodes above an epitaxial layer having a regular dopant concentration.

7. The semiconductor power device of claim 1 wherein:

said counter dopant region disposed in said JBS area having an epitaxial dopant concentration reduction ranging from twenty to eighty percents whereby performance parameters of said power transistor cell in said active cell area are not affected.

8. The semiconductor power device of claim 1 wherein:

said epitaxial layer further comprising an upper epitaxial layer having a reduced dopant concentration near a top surface encompassing said body-type-dopant regions formed by applying a blank body-type-dopant implant into an epitaxial layer having a regular dopant concentration.

9. The semiconductor power device of claim 1 wherein:

said Schottky diodes interspersed between body-type-dopant regions disposed in an epitaxial layer wherein said counter dopant region comprises a reduced epitaxial dopant region formed by applying a body-type-dopant implant through contact openings to form said counter-dopant regions surrounding said body-type-dopant regions for reducing said sudden reversal of dopant profile near said PN junction.

10. The semiconductor power device of claim 1 wherein:

said Schottky diodes configured as open stripes interspersed between body-type-dopant regions in said JBS area.

11. The semiconductor power device of claim 1 wherein:

said Schottky diodes configured as intersected stripes of body-type-dopant region surrounding square shaped Schottky contact regions in said JBS area.

12. The semiconductor power device of claim 1 wherein:

said Schottky diodes configured as peripheral stripes of body-type-dopant region surrounding hexagonal shaped Schottky contact regions in said JBS area.

13. The semiconductor power device of claim 1 wherein:

said Schottky diodes configured as peripheral stripes of body-type-dopant region surrounding polygon shaped Schottky contact regions in said JBS area.

14. The semiconductor power device of claim 1 wherein:

said Schottky diodes configured as peripheral areas of body-type-dopant region surrounding circular shaped Schottky contact regions in said JBS area.

15. The semiconductor power device of claim 1 further comprising:

gate buses formed extended from said active cell area to said JBS area as open combs whereby greater area of said JBS area is provided by not running said gate buses through a peripheral region around said JBS area.

16. A method for manufacturing a semiconductor power device with an active cell area having a plurality of power transistor cells and a junction barrier Schottky (JBS) area further comprising a step of:

forming a plurality of Schottky diodes by forming a plurality of PN junctions on an epitaxial layer near a top surface of a semiconductor substrate in said JBS area; and

forming a counter dopant region in said epitaxial layer near each of said PN junctions for reducing a sudden reversal of dopant profile near said PN junctions for preventing an early breakdown in said PN junction.

17. The method of claim 16 wherein:

said step of forming said counter dopant region in said epitaxial layer further comprising a step of forming an upper epitaxial layer having a reduced dopant concentration near a top surface encompassing said Schottky diodes above an epitaxial layer having a regular dopant concentration.

18. The method of claim 16 wherein:

said step of forming said counter dopant region in said JBS area further comprising a step of forming in said JBS area an epitaxial dopant-concentration reduction regions having an epitaxial dopant concentration ranging from twenty to eighty percents of a regular epitaxial dopant concentration whereby performance parameters of said power transistor cell in said active cell area are not affected.

19. The method of claim 16 wherein:

said step of forming said counter dopant region in said epitaxial layer further comprising a step of applying a blank body-type-dopant implant into an epitaxial layer to form an upper epitaxial layer having a reduced dopant concentration near a top surface encompassing said Schottky diodes.

20. The method of claim 16 wherein:

said step of forming said counter dopant region in said JBS area further comprising a step of applying a body-type-dopant implant through contact openings to form said counter-dopant regions surrounding said body-type-dopant regions for reducing said sudden reversal of dopant profile near said PN junction.

21. The method of claim 16 further comprising a step of:

forming said Schottky diodes as open stripes interspersed between body-type-dopant regions in said JBS area.

22. The method of claim 16 further comprising a step of:

forming said Schottky diodes as intersected stripes of body-type-dopant region surrounding square shaped epitaxial dopant regions in said JBS area.

23. The method of claim 16 further comprising a step of:

forming said Schottky diodes as peripheral stripes of body-type-dopant region surrounding hexagonal shaped epitaxial dopant regions in said JBS area.

24. The method of claim 16 further comprising a step of:

forming said Schottky diodes as peripheral stripes of body-type-dopant region surrounding polygon shaped epitaxial dopant regions in said JBS area.

25. The method of claim 16 further comprising a step of:

forming said Schottky diodes as peripheral areas of body-type-dopant region surrounding circular shaped epitaxial dopant regions in said JBS area.

26. The method of claim 16 further comprising a step of:

forming gate buses to extend from said active cell area to said JBS area as open combs whereby greater area of said JBS area is provided by not running said gate buses through a peripheral region around said JBS area.

27. A semiconductor power device comprising an active cell area having a plurality of power transistor cells and a Junction Barrier controlled Schottky (JBS) area wherein:

said JBS area comprising a plurality of Schottky diodes each interspersed between a plurality of PN junctions wherein each said PN junction comprising a body-type-dopant region disposed on an epitaxial layer near a top surface of a semiconductor substrate; and

wherein said body-type-dopant regions further comprising a heavy body-type-dopant region and a light body-type-dopant region surrounding said heavy body-type-dopant region for reducing a sudden reversal of dopant profile near said PN junctions for preventing an early breakdown in said PN junction.

28. The semiconductor power device of claim 27 wherein:

said body-type-dopant regions comprising a P-type-dopant disposed in a N-type-dopant epitaxial layer.

29. The semiconductor power device of claim 27 wherein:

said semiconductor power device further comprising a metal oxide semiconductor field effect transistor (MOSFET) device.

30. The semiconductor power device of claim 27 wherein:

said semiconductor power device further comprising a trenched metal oxide semiconductor field effect transistor (MOSFET) device wherein said active cell area comprising a plurality of MOSFET cells.

31. The semiconductor power device of claim 27 wherein:

said epitaxial layer further comprising an upper epitaxial layer having a reduced dopant concentration near a top surface encompassing said Schottky diodes above an epitaxial layer having a regular dopant concentration.

32. The semiconductor power device of claim 27 wherein:

said counter dopant region disposed in said JBS area having an epitaxial dopant concentration reduction ranging from twenty to eighty percents whereby performance parameters of said power transistor cell in said active cell area are not affected.

33. The semiconductor power device of claim 27 wherein:

said Schottky diodes configured as open stripes interspersed between body-type-dopant regions in said JBS area.

34. The semiconductor power device of claim 27 wherein:

said Schottky diodes configured as intersected stripes of body-type-dopant region surrounding square shaped Schottky contact regions in said JBS area.

35. The semiconductor power device of claim 27 wherein:

said Schottky diodes configured as peripheral stripes of body-type-dopant region surrounding hexagonal shaped Schottky contact regions in said JBS area.

36. The semiconductor power device of claim 27 wherein:

said Schottky diodes configured as peripheral stripes of body-type-dopant region surrounding polygon shaped Schottky contact regions in said JBS area.

37. The semiconductor power device of claim 27 wherein:

said Schottky diodes configured as peripheral areas of body-type-dopant region surrounding circular shaped Schottky contact regions in said JBS area.

38. The semiconductor power device of claim 27 further comprising:

gate buses formed extended from said active cell area to said JBS area as open combs whereby greater area of said JBS area is provided by not running said gate buses through a peripheral region around said JBS area.

39. The semiconductor power device of claim 27 further comprising:

a macro cell structure wherein each macro cell comprises a plurality of MOSFET cells and a JBS area.