Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions

• US 7,436,026 B2
• Filed: 09/14/2004
• Issued: 10/14/2008
• Est. Priority Date: 06/26/2003
• Status: Expired due to Term

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Kreps, Scott A.
• Primary Examiner(s): Pham; Long
• Application Number:
  US10/940,426
• Publication Number:
  US 20050087737A1
• Time in Patent Office: 1,491 Days
• Field of Search: 257/344, 257/346, 257/408, 257/18, 257/20
• US Class Current: 257/344
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The at least one MOSFET may include spaced apart source and drain regions in the semiconductor substrate, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. The superlattice channel may have upper surface portions vertically stepped above adjacent upper surface portions of the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor. The at least one MOSFET may additionally include a gate overlying the superlattice channel.

Claims

1. A semiconductor device comprising:

a semiconductor substrate; and

at least one metal oxide semiconductor field-effect transistor (MOSFET) comprising

spaced apart source and drain regions in said semiconductor substrate,

a superlattice channel comprising a plurality of stacked groups of layers on said semiconductor substrate between said source and drain regions, and having upper surface portions being vertically stepped above adjacent upper surface portions of said source and drain regions,

each group of layers of said superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon,

said energy-band modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing semiconductor portions being chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween, the non-semiconductor selected from the group consisting of at least one of oxygen, nitrogen, fluorine, and carbon, and

a gate overlying said superlattice channel.

2. The semiconductor device of claim 1 wherein said semiconductor substrate comprises an underlying portion aligned with said superlattice channel.

3. The semiconductor device of claim 1 wherein said gate comprises a gate oxide layer and a gate electrode thereover;

and wherein said superlattice channel is aligned with said gate electrode.

4. The semiconductor device of claim 1 wherein said gate comprises a gate oxide layer, a gate electrode thereover, and sidewall spacers on opposing sides of said gate electrode;

and wherein said superlattice channel is aligned with said sidewall spacers.

5. The semiconductor device of claim 1 wherein said at least one MOSFET comprises a plurality thereof;

and further comprising an isolation region in said semiconductor substrate between adjacent MOSFETs.

6. The semiconductor device of claim 1 further comprising a contact layer on at least one of said source and drain regions.

7. The semiconductor device of claim 1 wherein said superlattice channel has a common energy band structure therein.

8. The semiconductor device of claim 1 wherein said superlattice channel has a higher charge carrier mobility than would otherwise be present without said non-semiconductor layer.

9. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

10. The semiconductor device of claim 1 wherein each base semiconductor portion comprises germanium.

11. The semiconductor device of claim 1 wherein each energy band-modifying layer consists of oxygen.

12. The semiconductor device of claim 1 wherein each energy band-modifying layer is a single monolayer thick.

13. The semiconductor device of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.

14. The semiconductor device of claim 1 wherein said superlattice further has a substantially direct energy bandgap.

15. The semiconductor device of claim 1 wherein said superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

16. The semiconductor device of claim 1 wherein all of said base semiconductor portions are a same number of monolayers thick.

17. The semiconductor device of claim 1 wherein at least some of said base semiconductor portions are a different number of monolayers thick.

18. A semiconductor device comprising:

a semiconductor substrate; and

at least one metal oxide semiconductor field-effect transistor (MOSFET) comprising

spaced apart source and drain regions in said semiconductor substrate,

a superlattice channel comprising a plurality of stacked groups of layers on said semiconductor substrate between said source and drain regions, and having upper surface portions being vertically stepped above adjacent upper surface portions of said source and drain regions,

each group of layers of said superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon,

said energy-band modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing semiconductor portions being chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween, the non-semiconductor selected from the group consisting of at least one of oxygen, nitrogen, fluorine, and carbon, and

a gate comprising a gate oxide layer overlying said superlattice channel and a gate electrode thereover, and said gate electrode being aligned with said superlattice channel;

said semiconductor substrate comprising an underlying portion aligned with said superlattice channel.

19. The semiconductor device of claim 18 wherein said at least one MOSFET comprises a plurality thereof;

and further comprising an isolation region in said semiconductor substrate between adjacent MOSFETs.

20. The semiconductor device of claim 18 further comprising a contact layer on at least one of said source and drain regions.

21. The semiconductor device of claim 18 wherein said superlattice channel has a common energy band structure therein.

22. The semiconductor device of claim 18 wherein said superlattice channel has a higher charge carrier mobility than would otherwise be present without said non-semiconductor layer.

23. The semiconductor device of claim 18 wherein each base semiconductor portion comprises silicon.

24. The semiconductor device of claim 18 wherein each base semiconductor portion comprises germanium.

25. The semiconductor device of claim 18 wherein each energy band-modifying layer consists of oxygen.

26. The semiconductor device of claim 18 wherein each energy band-modifying layer is a single monolayer thick.

27. The semiconductor device of claim 18 wherein each base semiconductor portion is less than eight monolayers thick.

28. The semiconductor device of claim 18 wherein said superlattice further has a substantially direct energy bandgap.

29. The semiconductor device of claim 18 wherein said superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

30. The semiconductor device of claim 18 wherein all of said base semiconductor portions are a same number of monolayers thick.

31. The semiconductor device of claim 18 wherein at least some of said base semiconductor portions are a different number of monolayers thick.

32. A semiconductor device comprising:

a semiconductor substrate; and

at least one metal oxide semiconductor field-effect transistor (MOSFET) comprising

spaced apart source and drain regions in said semiconductor substrate,

a superlattice channel comprising a plurality of stacked groups of layers on said semiconductor substrate between said source and drain regions, and having upper surface portions being vertically stepped above adjacent upper surface portions of said source and drain regions,

each group of layers of said superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon,

said energy-band modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing semiconductor portions being chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween, the non-semiconductor selected from the group consisting of at least one of oxygen, nitrogen, fluorine, and carbon, and

a gate comprising a gate oxide layer overlying said superlattice channel, a gate electrode thereover, and sidewall spacers on opposing sides of said gate electrode, said sidewall spacers being aligned with said superlattice channel;

said semiconductor substrate comprising an underlying portion aligned with said superlattice channel.

33. The semiconductor device of claim 32 wherein said at least one MOSFET comprises a plurality thereof;

and further comprising an isolation region in said semiconductor substrate between adjacent MOSFETs.

34. The semiconductor device of claim 32 further comprising a contact layer on at least one of said source and drain regions.

35. The semiconductor device of claim 32 wherein said superlattice channel has a common energy band structure therein.

36. The semiconductor device of claim 32 wherein said superlattice channel has a higher charge carrier mobility than would otherwise be present without said non-semiconductor layer.

37. The semiconductor device of claim 32 wherein each base semiconductor portion comprises silicon.

38. The semiconductor device of claim 32 wherein each base semiconductor portion comprises germanium.

39. The semiconductor device of claim 32 wherein each energy band-modifying layer consists of oxygen.

40. The semiconductor device of claim 32 wherein each energy band-modifying layer is a single monolayer thick.

41. The semiconductor device of claim 32 wherein each base semiconductor portion is less than eight monolayers thick.

42. The semiconductor device of claim 32 wherein said superlattice further has a substantially direct energy bandgap.

43. The semiconductor device of claim 32 wherein said superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

44. The semiconductor device of claim 32 wherein all of said base semiconductor portions are a same number of monolayers thick.

45. The semiconductor device of claim 32 wherein at least some of said base semiconductor portions are a different number of monolayers thick.