Semiconductor integrated circuit comprising read only memory, semiconductor device comprising the semiconductor integrated circuit, and manufacturing method of the semiconductor integrated circuit

• US 7,436,032 B2
• Filed: 12/17/2004
• Issued: 10/14/2008
• Est. Priority Date: 12/19/2003
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US11/013,376
• Publication Number:
  US 20050133790A1
• Time in Patent Office: 1,397 Days
• Field of Search: 257390-392
• US Class Current: 257/390
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 21/76894 using a laser, e.g. laser cutting, laser direct writing, laser repair
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/38 Doping programmed, e.g. mask ROM
• CPC Class Codes: H10B 20/65 of memory structures of the ROM only type

Abstract

A chip with increased impact resistance, attractive design and reduced cost, and a manufacturing method thereof are provided. A semiconductor integrated circuit is formed on a large glass substrate, and a part of data of a ROM included therein is determined by an ink jet method or a laser cutting method. Accordingly, the cost can be reduced without requiring a photomask, resulting in an inexpensive ID chip. Further, depending on the application, the semiconductor integrated circuit is transposed to a flexible substrate, thereby an ID chip with improved impact resistance and more attractive design can be achieved.

Claims

1. A semiconductor device comprising:

a semiconductor integrated circuit comprising;

an insulating substrate;

a memory cell formed over the insulating substrate and connected to a wiring including a cut portion obtained by laser cutting; and

a connecting terminal, and

an antenna that is connected to the connecting terminal and formed over the semiconductor integrated circuit.

2. A semiconductor device according to claim 1, wherein the insulating substrate is one of a glass substrate and a flexible substrate.

3. A semiconductor device according to claim 1, wherein the antenna includes gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), nickel (Ni), tantalum (Ta), bismuth (Bi), lead (Pb), indium (In), tin (Sn), zinc (Zn), titanium (Ti), aluminum (Al), or an alloy of them.

4. A card comprising a semiconductor device according to claim 1.

5. A tag comprising a semiconductor device according to claim 1.

6. A semiconductor device comprising:

a semiconductor integrated circuit comprising;

a first read only memory that includes a memory cell connected to a wiring formed by a photomask;

a second read only memory connected to a wiring including a cut portion obtained by laser cutting; and

a connecting terminal,

wherein the first read only memory and the second read only memory are formed on an insulating substrate, and

an antenna that is connected to the connecting terminal and formed over the semiconductor integrated circuit.

7. A semiconductor device according to claim 6, wherein the insulating substrate is one of a glass substrate and a flexible substrate.

8. A semiconductor device according to claim 6, wherein the antenna includes gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), nickel (Ni), tantalum (Ta), bismuth (Bi), lead (Pb), indium (In), tin (Sn), zinc (Zn), titanium (Ti), aluminum (Al), or an alloy of them.

9. A card comprising a semiconductor device according to claim 6.

10. A tag comprising a semiconductor device according to claim 6.

11. A semiconductor device comprising:

a semiconductor integrated circuit comprising;

an insulating substrate;

a read only memory over the insulating substrate including a memory cell connected to a wiring; and

a connecting terminal,

wherein the wiring comprise aggregate of grains formed by a plurality of metal particles, and

an antenna that is connected to the connecting terminal and formed over the semiconductor integrated circuit.

12. A semiconductor device according to claim 11, wherein the metal particles comprise at least one material selected from the group consisting of gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), nickel (Ni), tantalum (Ta), bismuth (Bi), lead (Pb), indium (In), tin (Sn), zinc (Zn), titanium (Ti), aluminum (Al), and an alloy of them.

13. A semiconductor device comprising:

a semiconductor integrated circuit comprising;

an insulating substrate;

a memory cell formed over the insulating substrate, the memory cell comprising a thin film transistor;

a first wiring connected to a source of the thin film transistor;

a second wiring connected to a drain of the thin film transistor; and

a connecting terminal,

wherein at least one of the first wiring and the second wiring includes a cut portion obtained by laser cutting, and

an antenna that is connected to the connecting terminal and formed over the semiconductor integrated circuit.

14. A semiconductor device according to claim 13,

wherein one of the first wiring and the second wiring is connected to a VDD, and the other is cut so as to be disconnected to a GND.

15. A semiconductor device according to claim 13,

wherein one of the first wiring and the second wiring is connected to a GND, and the other is cut so as to be disconnected to a VDD.

16. A semiconductor device according to claim 13, wherein the insulating substrate is one of a glass substrate and a flexible substrate.

17. A semiconductor device according to claim 13, wherein the antenna includes gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), nickel (Ni), tantalum (Ta), bismuth (Bi), lead (Pb), indium (In), tin (Sn), zinc (Zn), titanium (Ti), aluminum (Al), or an alloy of them.

18. A card comprising a semiconductor device according to claim 13.

19. A tag comprising a semiconductor device according to claim 13.

20. A semiconductor device comprising:

a semiconductor integrated circuit comprising;

a first read only memory that includes a memory cell connected to a wiring formed by a photomask;

a second read only memory comprising a thin film transistor;

a first wiring connected to a source of the thin film transistor;

a second wiring connected to a drain of the thin film transistor; and

a connecting terminal,

wherein at least one of the first wiring and the second wiring includes a cut portion obtained by laser cutting, and

wherein the first read only memory and the second read only memory are formed on an insulating substrate, and

an antenna that is connected to the connecting terminal and formed over the semiconductor integrated circuit.

21. A semiconductor device according to claim 20,

wherein one of the first wiring and the second wiring is connected to a VDD, and the other is cut so as to be disconnected to a GND.

22. A semiconductor device according to claim 20,

wherein one of the first wiring and the second wiring is connected to a GND, and the other is cut so as to be disconnected to a VDD.

23. A semiconductor device according to claim 20, wherein the insulating substrate is one of a glass substrate and a flexible substrate.

24. A semiconductor device according to claim 20, wherein the antenna includes gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), nickel (Ni), tantalum (Ta), bismuth (Bi), lead (Pb), indium (In), tin (Sn), zinc (Zn), titanium (Ti), aluminum (Al), or an alloy of them.

25. A card comprising a semiconductor device according to claim 20.

26. A tag comprising a semiconductor device according to claim 20.