Visible/near infrared image sensor array
First Claim
1. A MOS or CMOS based visible/near infrared sensor array comprising:
- A) a substrate,B) a plurality of MOS or CMOS pixel circuits fabricated in or on said substrate, each pixel circuit comprising;
1) a charge collecting electrode for collecting electrical charges and2) a plurality of transistors for monitoring periodically charges collected by said charge collecting electrode,C) a continuous un-pixelated photodiode layer of charge generating material located above said pixel circuits for converting into electrical charges electromagnetic radiation in the visible and near infrared spectral ranges, said photodiode layer comprising at least an n-layer, an intrinsic layer and a p-layer,wherein each of the n-layer, the intrinsic layer and the p-layer of the continuous un-pixelated photodiode layer are continuous with no gaps between pixels, andwherein one of said n-layer or said p-layer is adjacent to the charge collecting electrodes in each of the pixel circuits to define a bottom layer; and
wherein the bottom layer comprises sufficient carbon to increase its electrical resistance to more than 2×
107 ohm-cm to minimize pixel-to-pixel crosstalk; and
D) a surface electrode in the form of a grid or thin transparent layer located above said layer of charge generating material.
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Abstract
A MOS or CMOS sensor for high performance imaging in broad spectral ranges including portions of the infrared spectral band. These broad spectral ranges may also include portions or all of the visible spectrum, therefore the sensor has both daylight and night vision capabilities. The sensor includes a continuous multi-layer photodiode structure on a many pixel MOS or CMOS readout array where the photodiode structure is chosen to include responses in the near infrared spectral ranges. A preferred embodiment incorporates a microcrystalline copper indium diselenide/cadmium sulfide photodiode structure on a CMOS readout array. An alternate preferred embodiment incorporates a microcrystalline silicon germanium photodiode structure on a CMOS readout array. Each of these embodiments provides night vision with image performance that greatly surpasses the GEN III night vision technology in terms of enhanced sensitivity, pixel size and pixel count. Further advantages of the invention include low electrical bias voltages, low power consumption, compact packaging, and radiation hardness. In special preferred embodiments CMOS stitching technology is used to provide multi-million pixel focal plane array sensors. One embodiments of the invention made without stitching is a two-million pixel sensor. Other preferred embodiments available using stitching techniques include sensors with 250 million (or more) pixels fabricated on a single wafer. A particular application of these very high pixel count sensors is as a focal plane array for a rapid beam steering telescope in a low earth orbit satellite useful for tracking over a 1500-meter wide track with a resolution of 0.3 meter.
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Citations
26 Claims
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1. A MOS or CMOS based visible/near infrared sensor array comprising:
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A) a substrate, B) a plurality of MOS or CMOS pixel circuits fabricated in or on said substrate, each pixel circuit comprising; 1) a charge collecting electrode for collecting electrical charges and 2) a plurality of transistors for monitoring periodically charges collected by said charge collecting electrode, C) a continuous un-pixelated photodiode layer of charge generating material located above said pixel circuits for converting into electrical charges electromagnetic radiation in the visible and near infrared spectral ranges, said photodiode layer comprising at least an n-layer, an intrinsic layer and a p-layer, wherein each of the n-layer, the intrinsic layer and the p-layer of the continuous un-pixelated photodiode layer are continuous with no gaps between pixels, and wherein one of said n-layer or said p-layer is adjacent to the charge collecting electrodes in each of the pixel circuits to define a bottom layer; and wherein the bottom layer comprises sufficient carbon to increase its electrical resistance to more than 2×
107 ohm-cm to minimize pixel-to-pixel crosstalk; andD) a surface electrode in the form of a grid or thin transparent layer located above said layer of charge generating material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification