Virtual test head for IC

• US 7,436,197 B1
• Filed: 09/23/2004
• Issued: 10/14/2008
• Est. Priority Date: 09/23/2004
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Jacobson, Steven
• Primary Examiner(s): Nguyen; Vinh P
• Application Number:
  US10/950,285
• Time in Patent Office: 1,482 Days
• Field of Search: 324760-765, 324/158.1, 324/73.1, 702120-127, 714724-733
• US Class Current: 324/756.02
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture

Abstract

In a test system for a semiconductor device, the device under test (DUT) is remotely located relative to the tester that generates the test vector signals. The tester and remotely located DUT are connected by a serial connection and each includes a serializer-deserializer for converting outgoing data to serial form and deserializing incoming data.

Claims

1. A method of testing a semiconductor device (DUT) using a tester, comprising

locating the DUT in a first DUT socket mounted on a first board at a remote location remote from the tester, and

providing communication means for serially communicating between the tester and the DUT for transferring information between the tester and the DUT, the tester including a second DUT socket and an adaptor board located remotely from the first board, the adaptor board being adapted to be mounted on the second DUT socket and including a serializer-deserializer (SERDES) as part of the communication means.

2. A method of claim 1, wherein the information transferred from the tester to the DUT is test vector pattern data, and the information transferred from the DUT to the tester is output data from output pins of the DUT.

3. A method of claim 2, wherein the tester and DUT are connected by an intranet or Internet connection.

4. A method of claim 3, wherein providing the communication means includes providing said serializer-deserializer (SERDES) located at the tester and providing a second SERDES located at the DUT.

5. A method of claim 4, wherein the first DUT socket for the DUT and the second SERDES are mounted on a printed circuit board.