Three-dimensional ladar module with alignment reference insert circuitry

• US 7,436,494 B1
• Filed: 02/15/2007
• Issued: 10/14/2008
• Est. Priority Date: 03/28/2003
• Status: Expired

• Current Assignee: Longhorn Automotive Group LLC (Alpha Alpha Intellectual Partners LLC)
• Original Assignee: Irvine Sensors Corp.
• Inventors: Ludwig, David, Kennedy, John, Krutzik, Christian
• Primary Examiner(s): Tarcza; Thomas H.
• Assistant Examiner(s): Ratcliffe; Luke D
• Application Number:
  US11/706,724
• Time in Patent Office: 607 Days
• Field of Search: 356 401- 41, 356 301- 315, 356 501- 515, 356 6- 22
• US Class Current: 356/4.01
• CPC Class Codes: G01S 17/42 Simultaneous measurement of distance and other co-ordinates indirect measurement G01S17/46
• CPC Class Codes: G01S 17/894 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
• CPC Class Codes: G01S 7/4863 Detector arrays, e.g. charge-transfer gates
• CPC Class Codes: G01S 7/487 Extracting wanted echo signals , e.g. pulse detection
• CPC Class Codes: G01S 7/51 Display arrangements

Abstract

A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source such as a laser is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO shift register range bin. Dependant on the value of the digit contained in the bins in the register, and the digit'"'"'s bin location, the time of a photon reflection from a target surface can be determined. A T₀ trigger signal defines the reflection time represented at each bin location by resetting appropriate circuitry to begin processing.

A reference insert circuit inserts data into the FIFO registers at a preselected location to provide a reference point at which all FIFO shift register data may be aligned to accommodate for timing differences between layers and channels. The bin data representing the photon reflections from the various target surfaces are read out of the FIFO and processed using appropriate circuitry such as a field programmable gate array to create a synchronized 3-D point cloud for creating a 3-D target image.

Claims

1. An electronic circuit comprised of:

photon detector array means for converting photons to a detector output signal,

a plurality of readout electronics integrated circuit chips, each readout electronics integrated circuit chip comprising a plurality of channels for receiving and processing output signals generated by said photon detector array,

wherein said plurality of readout electronics integrated circuit chips are arranged in a stacked configuration with each of said readout electronics integrated circuit chips forming one layer of said stacked configuration,

wherein said photon detector array is bonded to a lateral surface of said stacked configuration perpendicular to said stacked configuration and connected to the plurality of channels via a plurality of T-connects disposed on said lateral surface of said stacked configuration,

wherein at least two of said channels comprise,

converting circuit means for converting said detector output signal to a digitized data value comprised of one or more digital bits comprising an image data set wherein each digital bit has a position in said image data set,

reference insert circuit means for inserting one or more user-defined reference points at one or more predetermined positions in said image data set, and,

reference point synchronization circuit means for synchronizing at least one of said user-defined reference points with at least one other of said user-defined reference points in each of at least two of said channels'"'"' image data sets.

2. The electronic circuit of claim 1 comprising at least one FIFO shift register for storing said image data set.

3. The electronic circuit of claim 1 where said reference point synchronization means is a field programmable gate array.

4. The electronic circuit of claim 1 wherein said two channels are each defined upon one integrated circuit chip.

5. The electronic circuit of claim 1 wherein each of said two channels are defined upon separate integrated circuit chips.

6. An electronic circuit comprised of:

an electronic sensor having an output,

a plurality of readout electronics integrated circuit chips, each readout electronics integrated circuit chip comprising a plurality of channels for receiving and processing output signals generated by said photon detector array,

wherein said plurality of readout electronics integrated circuit chips are arranged in a stacked configuration with each of said readout electronics integrated circuit chips forming one layer of said stacked configuration,

wherein said photon detector array is bonded to a lateral surface of said stacked configuration perpendicular to said stacked configuration and connected to the plurality of channels via a plurality of T-connects disposed on said lateral surface of said stacked configuration,

wherein at least two of said layers comprise sensor converting means for converting the output of said electronic sensor to a digitized data value,

storage circuit means for the storing of said digitized data value,

said storage circuit means comprising a plurality of individual bin circuit means, each of said bin circuit means having a variable logic state and each having a storage circuit means position,

a reference insert circuit for selectively asserting a predetermined bin logic state in said at least one preselected bin circuit means whereby a user-defined reference point may be selectively asserted at the respective storage circuit means positions on each of said layers,

output circuit means for the outputting of said digitized data value, and,

reference point synchronization circuit means for the receiving of and synchronizing of said outputted digitized data values using said reference points for generating a plurality of synchronized digitized data values.

7. The electronic circuit of claim 6 wherein said storage circuit means is comprised of a FIFO shift register.

8. The electronic circuit of claim 6 wherein said synchronizing is performed in a field programmable gate array.