Nonvolatile semiconductor memory device

• US 7,436,699 B2
• Filed: 12/27/2006
• Issued: 10/14/2008
• Est. Priority Date: 01/10/2006
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Hidaka, Hideto, Murai, Yasumitsu, Tanizaki, Hiroaki, Tsuji, Takaharu
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US11/645,610
• Publication Number:
  US 20070159870A1
• Time in Patent Office: 657 Days
• Field of Search: 365/158, 365/173
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/5607 using magnetic storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.

Claims

1. A nonvolatile semiconductor memory device comprising:

a plurality of memory cells, arranged in rows and columns, each having a storing portion having a resistance value set according to storage data;

a plurality of bit lines, arranged corresponding to the respective memory cell columns, each connected to the memory cells in a corresponding column;

a plurality of source lines, arranged corresponding to the memory cell rows, each connected to the memory cells in a corresponding row;

write circuitry for transmitting a voltage corresponding to write data to a bit line on a selected column in data writing; and

source line drive circuitry for driving a source line on a selected row to first and second voltage levels in a predetermined sequence in said data writing, according to a current flowing between the bit line in said selected column and the source line in said selected row via a corresponding memory cell, the storing portion of the corresponding memory cell having the resistance value set, wherein

said write circuitry writes multiple bits of data in parallel;

said nonvolatile semiconductor memory device further comprises;

a column select circuit for selecting in parallel a plurality of columns equal in number to a bit width of the data to be written; and

said source line drive circuitry drives the source line common to the memory cells on the plurality of selected columns in said predetermined sequence.

2. The nonvolatile semiconductor memory device according to claim 1, wherein

said source line drive circuitry drives the source line in the selected row from opposite ends.

3. The nonvolatile semiconductor memory device according to claim 1, wherein

the source line is arranged to be shared by the memory cells in adjacent columns.

4. The nonvolatile semiconductor memory device according to claim 1, wherein

each of the memory cells further includes an access transistor for coupling, when made conductive, a corresponding storing portion to a corresponding source line;

and

said nonvolatile semiconductor memory device further comprises;

a plurality of word lines, arranged corresponding to the memory cell rows, each connected to the access transistors of the memory cells in a corresponding row, and

a word line select drive circuit for driving a word line in the selected row to the selected state; and

said word line select drive circuit is arranged in a region opposing in a row direction to the source line drive circuitry.

5. The nonvolatile semiconductor memory device according to claim 1, wherein

the memory cells are arranged such that the storing portions arranged in a row direction are greater in number than the storing portions arranged in a column direction.

6. The nonvolatile semiconductor memory device according to claim 1, wherein

each memory cell further includes an access transistor for coupling, when made conductive, a corresponding storing portion to a corresponding source line;

and

said nonvolatile semiconductor memory device further comprises;

a plurality of word lines, arranged corresponding to the memory cell rows, each being connected to the access transistors of the memory cells in a corresponding row, and

a word line drive circuit for driving a word line in the selected row to a selected state at the voltage level higher than a high-level voltage that can be supplied by said source line select drive circuitry and said write circuitry.

7. The nonvolatile semiconductor memory device according to claim 1, wherein

said source line select drive circuitry maintains an unselected source line at a voltage level corresponding to a logical level of a low voltage.

8. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a write data line for transferring the write data from said write circuitry;

a plurality of column select gates, arranged corresponding to the respective bit lines, for coupling corresponding bit lines to the write data line, when made conductive; and

a column select signal producing circuit for producing a column select signal turning on the column select gate corresponding to a selected column according to an address signal, said column select signal, when selected, being set to a voltage level higher than levels of voltages supplied to the source lines and the bit lines.

9. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a bit line voltage setting circuit for setting an unselected bit line to a voltage level corresponding to a voltage level of the selected source line on the selected row in a data write mode.

10. A nonvolatile semiconductor memory device comprising:

a plurality of memory cells, arranged in rows and columns, each having a storing portion having a resistance value set according to storage data;

a plurality of bit lines, arranged corresponding to the respective memory cell columns, each connected to the memory cells in a corresponding column;

a plurality of source lines, arranged corresponding to the memory cell rows, each connected to the memory cells in a corresponding row;

write circuitry for transmitting a voltage corresponding to write data to a bit line on a selected column in data writing; and

source line drive circuitry for driving a source line on a selected row to a first and second voltage levels in a predetermined sequence in said data writing, according to a current flowing between the bit line in said selected column and the source line in said selected row via a corresponding memory cell, the storing portion of the corresponding memory cell having the resistance value set, wherein

each of the memory cells further includes first and second access transistors each for connecting a corresponding storing portion to a corresponding source line; and

said nonvolatile semiconductor memory device further comprises;

a plurality of first gate lines, arranged corresponding to the memory cell rows, each connected to the first access transistors of the memory cells in a corresponding row,

a plurality of second gate lines, arranged corresponding to the memory cell rows, each connected to the second access transistors of the memory cells in a corresponding row, and

a word line select drive circuit for driving both the first and second gate lines in said selected row to a selected state, each word line being constituted by the first gate line and the second gate line arranged on a corresponding row.

11. The nonvolatile semiconductor memory device according to claim 10, wherein

a set of the first gate line and the second gate line and the source line are arranged alternately in a column direction, and

said source line drive circuitry drives concurrently the source lines adjacent, respectively, to the first and second gate lines arranged on the selected row.

12. A nonvolatile semiconductor memory device comprising:

a plurality of memory cells, arranged in rows and columns, each having a storing portion having a resistance value set according to storage data;

a plurality of bit lines, arranged corresponding to the memory cell columns, each connected to the memory cells in a corresponding column;

a plurality of source lines, arranged corresponding to the memory cell rows, each connected to the memory cells in a corresponding row;

a column select circuit for concurrently selecting the columns equal in number to a bit width of multi-bit write data in data writing;

a write circuit for transmitting a first voltage to each of the bit lines on the selected columns regardless of a value of the write data bit, and then transmitting concurrently voltages corresponding to the write data bits to the bit lines in the selected columns, respectively in said data writing; and

a source line drive circuit for driving the source line in a selected row to a second voltage level and the first voltage level in a predetermined sequence in the data write operation, according to a current flowing between the bit line in the selected column and the source line in the selected row via a corresponding memory cell, the resistance value of said storing portion of the corresponding, selected memory cell being set, said source line drive circuit transmitting said second voltage concurrently with transmission of said first voltage by said write circuit, to set said storing portion of the selected memory cell to a resistance state corresponding to a predetermined logical level.

13. The nonvolatile semiconductor memory device according to claim 12, further comprising:

a bit line voltage setting circuit for setting an unselected bit line on an unselected column to a voltage level corresponding to a voltage level of the selected source line when said source line drive circuit transmits said second voltage.

14. A nonvolatile semiconductor memory device comprising:

a plurality of memory cells, arranged in rows and columns, each having a storing portion having a resistance value set according to storage data;

a plurality of bit lines, arranged corresponding to the memory cell columns, each connected to the memory cells on a corresponding column;

a plurality of source lines each arranged being shared by the memory cells in a plurality of columns;

a source line drive circuit for changing a voltage level of the source line on a selected column in a predetermined sequence in data writing; and

a data write circuit having at least a time period for driving the bit line on the selected column according to the write data in the data writing, wherein

the write data comprises multiple bits, and

the plurality of columns sharing the source line are equal in number to a bit width of said multi-bit data.

15. The nonvolatile semiconductor memory device according to claim 14, wherein

each source line includes:

a main line portion arranged extending in a column direction and corresponding to a predetermined plurality of columns, and

a plurality of feeder line portions, arranged corresponding to the memory cell rows, each connected to the memory cells located on a corresponding row and said predetermined plurality of columns, as well as to said main line portion.

16. The nonvolatile semiconductor memory device according to claim 15, wherein

each feeder line portion is arranged being shared by the memory cells in adjacent rows.

17. The nonvolatile semiconductor memory device according to claim 15, wherein

each memory cell further includes first and second access transistors arranged in parallel with respect to said storing portion,

each word line includes a first gate line connected to the first access transistor of the memory cell on a corresponding row, and a second gate line connected to a second access transistor of the memory cell in the corresponding row, and

the feeder line portion is arranged alternately to a set of the first gate line and the second gate line.