NAND memory device column charging

• US 7,436,708 B2
• Filed: 03/01/2006
• Issued: 10/14/2008
• Est. Priority Date: 03/01/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US11/276,480
• Publication Number:
  US 20070206422A1
• Time in Patent Office: 958 Days
• Field of Search: 365/185.18, 365/205
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read timing. Devices and methods charge the array columns at pre-charge and following array access operations.

Claims

1. A method of operating a NAND flash memory device comprising:

powering up the memory device in response to an externally supplied power;

charging all colunm bit lines of first and second data pages of an array of the memory to a predetermined positive voltage level following powering up;

performing a read operation on the first data page while all column bit lines of the second data page are charged to the predetermined positive voltage level,

wherein the read operation comprises;

accessing a row of memory cells by activating a word line conductor of the first data page; and

sensing a voltage potential of column bit lines of the first data page after accessing the row; and

charging all column bit lines of the first data page to the predetermined positive voltage level following sensing the voltage potential of the column bit lines of the first data page.

2. The method of claim 1, further comprising storing multiple bits of data in a memory cell of the array using multiple voltage levels.

3. The method of claim 1, wherein charging includes charging all column bit lines of first and second data pages to about one volt.

4. A method of operating a NAND flash memory device comprising:

charging all column bit lines of first and second data pages of an array of the memory to a predetermined positive voltage level prior to performing an array access operation;

performing a read operation on the first data page while all column bit lines of the second data page are charged to the predetermined positive voltage level; and

powering up the memory device in response to an externally supplied power, and wherein charging all column bit lines of the first and second data pages is performed as a step of powering up the memory device.

5. The method of claim 4 wherein the read operation comprises:

accessing a row of memory cells by activating a word line conductor of the first data page; and

sensing a voltage potential of column bit lines of the first data page after accessing the row.

6. The method of claim 4, wherein charging includes supplying the predetermined voltage to the column bit lines of first and second data pages with a voltage regulator circuit.

7. The method of claim 6, wherein charging includes charging all column bit lines of first and second data pages to about one volt.

8. A method of operating a NAND flash memory device comprising:

powering up the memory device in response to an externally supplied power;

charging all column bit lines of first and second data pages of an array of the memory to a predetermined positive voltage level following powering up;

performing a read operation on the first data page while all column bit lines of the second data page are charged to the predetermined positive voltage level, wherein the read operation comprises accessing a row of memory cells by activating a word line conductor of the first data page, and sensing a voltage potential of column bit lines of the first data page after accessing the row; and

re-charging all column bit lines of the first data page to the predetermined positive voltage level following sensing the voltage potential of the column bit lines of the first data page.

9. The method of claim 8 wherein each memory cell of the array stores multiple bits of data using multiple voltage levels of the memory cell.

10. A NAND flash memory device comprising:

an array of memory cells arranged in accessible rows and columns, wherein each column of memory cells are coupled to a corresponding bit line;

control circuitry to perform a read operation on a column of the array of memory cells, wherein the read operation comprises sensing a voltage level of the bit line associated with the column being read, and charging the bit line to a predetermined voltage following sensing the voltage level of the bit line; and

wherein the control circuitry charges the bit line to the predetermined voltage during a power-up operation of the memory device.

11. The NAND flash memory device of claim 10 wherein the control circuitry maintains a charge on first and second adjacent bit lines located adjacent to and on opposite lateral sides of the bit line associated with the column being read while sensing the voltage level.

12. The NAND flash memory device of claim 10 wherein the predetermined voltage is provided by a voltage regulator circuit

13. A NAND flash memory device comprising:

an array of memory cells arranged in accessible rows and columns, wherein each column of memory cells are coupled to an associated bit line; and

control circuitry to perform a power-up operation on the memory in response to externally provided power, wherein the power-up operation comprises charging all column bit lines of first and second data pages of an array of the memory to a predetermined positive voltage level prior to initiating an array access operation.

14. The NAND flash memory device of claim 13 wherein the control circuitry performs a read operation on a column of the array of memory cells, wherein the read operation comprises sensing a voltage level of a bit line associated with the column being read, and charging the bit line to the predetermined voltage following sensing the voltage level of the bit line.

15. The NAND flash memory device of claim 13 wherein each memory cell of the array stores multiple bits of data using multiple voltage levels of the memory cell.

16. The NAND flash memory device of claim 13 wherein the control circuitry maintains a charge on first and second adjacent bit lines located adjacent to and on opposite lateral sides of the bit line associated with the column being read while sensing the voltage level.

17. The NAND flash memory device of claim 13 wherein the predetermined voltage is provided by a voltage regulator circuit.