Decision feedback equalizer and clock and data recovery circuit for high speed applications

• US 7,436,882 B2
• Filed: 02/09/2004
• Issued: 10/14/2008
• Est. Priority Date: 12/19/2003
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Momtaz, Afshin
• Primary Examiner(s): DEPPE, BETSY LEE
• Application Number:
  US10/774,965
• Publication Number:
  US 20050135510A1
• Time in Patent Office: 1,709 Days
• Field of Search: 375/233, 375/327, 375/340, 375/350, 375/376, 375/375, 327/156, 331/1.A, 331/1.R, 331/18, 331/25
• US Class Current: 375/233
• CPC Class Codes: H04B 10/2507 for the reduction or elimination of distortion or dispersion
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A method for communicating data includes equalizing received data to reduce channel related distortion in the received data. A clock having frequency and/or phase fixed relative to the equalized data is extracted from the equalized data. The extracted clock is used to clock a retimer to generate recovered data.

Claims

1. A communications system comprising:

a decision feedback equalizer adapted to reduce channel related distortion in received data, wherein the decision feedback equalizer is configured to generate equalized data; and

a clock and data recovery circuit coupled to the decision feedback equalizer, wherein the clock and data recovery circuit is configured to generate an extracted clock signal from the equalized data,

wherein the decision feedback equalizer includes;

a retimer that is configured to generate recovered equalized data from the equalized data in response to the extracted clock signal; and

a multiplier coupled to the retimer, the multiplier being configured to apply an equalization coefficient to the recovered equalized data to generate an equalized feedback signal;

wherein the clock and data recovery circuit is configured to iterate the equalization coefficient until the clock and data recovery circuit synchronizes with a frequency of the equalized data.

2. The communications system of claim 1 wherein the decision feedback equalizer comprises a summer that is configured to generate a combined signal by combining the equalized feedback signal with the received data.

3. The communications system of claim 2 wherein:

the decision feedback equalizer further comprises a slicer coupled to the summer, wherein the slicer is configured to generate the equalized data by converting the combined signal into a binary signal; and

the clock and data recovery circuit is configured to generate the extracted clock signal from the binary signal.

4. The communications system of claim 3 wherein:

the retimer comprises a flip-flop coupled to the slicer and to the clock and data recovery circuit; and

the flip-flop is configured to generate the recovered equalized data from the binary signal in response to the extracted clock signal.

5. The communications system of claim 3 wherein:

the clock and data recovery circuit comprises a frequency acquisition loop and a phase lock loop,

the frequency acquisition loop is configured to adjust a frequency of the extracted clock signal to maintain a fixed relationship between a frequency of a reference signal and the frequency of the extracted clock signal, and

the phase lock loop is configured to adjust a phase of the extracted clock signal to maintain a fixed relationship between a phase of the binary signal and the phase of the extracted clock signal.

6. The communications system of claim 5 wherein the clock and data recovery circuit further comprises a frequency lock detector configured to determine when the frequency of the extracted clock signal is fixed relative to the frequency of the reference signal.

7. The communications system of claim 1, wherein the equalization coefficient is based on a bit error rate of the received data.

8. The communications system of claim 1, wherein

the clock and data recovery circuit is configured to adjust the equalization coefficient based on a frequency difference exceeding a threshold, the frequency difference being based on a frequency of a reference clock included in the clock and data recovery circuit and a frequency of a divided signal, the divided signal being generated from the extracted clock signal.

9. A communications system comprising:

a decision feedback equalizer comprising;

a summer that is configured to combine an equalized feedback signal with the received data,

a slicer coupled to the summer, the slicer being configured to convert the combined signal to a binary signal,

a retimer coupled to the slicer, the retimer being configured to generate recovered equalized data from the binary signal in response to an extracted clock signal, and

a multiplier coupled to the retimer, the multiplier being configured to apply an equalization coefficient to the recovered equalized data to generate the equalized feedback signal, and

a clock and data recovery circuit coupled to the slicer, the clock and data recovery circuit being configured to;

generate the extracted clock signal from the binary signal; and

vary the equalization coefficient based on a difference between a divided frequency of the extracted clock signal and a frequency of a reference clock.

10. The communications system of claim 9 wherein:

the clock and data recovery circuit comprises a frequency acquisition loop and a phase lock loop, the frequency acquisition loop being configured to adjust the frequency of the extracted clock signal to maintain a fixed relationship between the frequency of the reference clock and the frequency of the extracted clock signal, and

the phase lock loop is configured to adjust a phase of the extracted clock signal to maintain a fixed relationship between a phase of the binary signal and the phase of the extracted clock signal.

11. The communications system of claim 10 wherein the clock and data recovery circuit further comprises a frequency lock detector configured to determine when the frequency of the extracted clock signal is fixed relative to the frequency of the reference clock.