Image processing device and method

• US 7,437,021 B2
• Filed: 12/11/2002
• Issued: 10/14/2008
• Est. Priority Date: 12/12/2001
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Satoh, Jin
• Primary Examiner(s): Ahmed; Samir A
• Assistant Examiner(s): Newman; Michael A
• Application Number:
  US10/467,543
• Publication Number:
  US 20040196290A1
• Time in Patent Office: 2,134 Days
• Field of Search: 345/502, 345/503, 345/504, 345/505, 345/506, 345/587, 345/582, 382/260, 382/283, 382/285, 382/302, 382/303, 382/304, 382/307, 700/4, 700/5
• US Class Current: 382/304
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/04 Texture mapping

Abstract

An image processing apparatus and method which can achieve a reduction in size of the crossbar circuit and achieve a higher speed of processing, which perform DDA processing (ST11), then read out texture data from a memory (ST12), perform sub-word reallocation processing (ST13), then perform texture-filtering (ST14), then globally distribute data by the crossbar circuit 13 to a first operation processing element of each processing module (ST15), then perform processing at the pixel level, specifically use the texture data after filtering and the various types of data after rasterization to perform operations by pixel units and draw the pixel data passing the various types of tests in the processing at the pixel level to a frame buffer on a memory module (ST16).

Claims

1. An image processing apparatus, comprising:

a plurality of processing modules configured to share processing data and perform parallel processing, the plurality of processing modules each comprising;

a memory module for storing at least data relating to filtering;

a processing circuit for obtaining data for filtering and performing assigned processing determined in advance by corresponding memory interleaving based on the processing data;

a first operation processing element for performing operation processing in pixel units based on assigned processing data and data after filtering; and

a second operation processing element for performing filtering based on the data for filtering and the data relating to filtering and receiving operation processing data from said first operation processing element, then drawing the operation processed data to the memory module; and

a crossbar circuit for connecting the first operation processing elements with the second operation processing elements of said processing modules, supplying the data for filtering obtained by the processing circuit in each processing module to the second operation processing element in the same processing module, supplying the data after filtering from the second operation processing element in each processing module to the first operation processing element in a predetermined processing module, and supplying the operation processing data from the first operation processing element of each processing module to the second operation processing element in the same processing module.

2. An image processing apparatus as set forth in claim 1, wherein the processing circuit of each processing module comprises a means for adjusting time so that the assigned processing is performed when the data after filtering is supplied to the first operation processing element.

3. An image processing apparatus as set forth in claim 1, further comprising a setup circuit for performing an operation on vertex data of a primitive, setting up one primitive, and outputting the assigned processing data to the processing circuits of the processing modules.

4. An image processing apparatus as set forth in claim 1, wherein the data for filtering is data relating to texture.

5. An image processing apparatus as set forth in claim 1, wherein said parallel processing is parallel processing at the pixel level.