Designing time-based measurement/control system

• US 7,437,265 B2
• Filed: 04/29/2005
• Issued: 10/14/2008
• Est. Priority Date: 04/29/2005
• Status: Expired due to Fees

• Current Assignee: Keysight Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Eidson, John C.
• Primary Examiner(s): Lau; Tung S
• Assistant Examiner(s): SUN, XIUQIN
• Application Number:
  US11/117,811
• Publication Number:
  US 20060247893A1
• Time in Patent Office: 1,264 Days
• Field of Search: 702/176, 711/112, 709/205, 709/250, 846/00, 370/393
• US Class Current: 702/176
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock

Abstract

A method for designing a measurement/control system that enables a system designer to explicitly specify the portions of a measurement/control system that are subject to a set of time constraints and the portions of the measurement/control system that are not directly subject to the set of time constraints. A method according to the present teachings includes determining an HRT/SRT boundary between a hard real-time (HRT) portion of a measurement/control system and a soft real-time (SRT) portion of the measurement/control system and determining a buffer for the HTR/SRT boundary in response to a set of time constraints associated with the HRT portion.

Claims

1. A method for designing a system, comprising:

specifying a boundary between a hard real-time (HRT) portion of the system and a soft real-time (SRT) portion of the system;

determining a set of parameters for a buffer for the boundary in response to a set of time constraints associated with the HRT portion;

using the set of parameters in designing the system; and

generating a time-script that specifies a set of parameters for a set of behaviors of the HRT portion.

2. The method of claim 1, wherein specifying a boundary includes specifying a boundary between a front-end and a back-end in an instrument.

3. The method of claim 1, wherein specifying a boundary includes specifying a boundary between a set of channels in a front-end of an instrument.

4. The method of claim 1, wherein specifying a boundary includes specifying a boundary in a communication mechanism in the system.

5. The method of claim 1, wherein determining a set of parameters for a buffer includes determining a capacity for the buffer.

6. The method of claim 1, further comprising altering the boundary at run-time.

7. The method of claim 1, further comprising simulating an operation of the buffer in response to the time constraints.

8. The method of claim 1, further comprising allocating a set of tasks of an application program in the system across the boundary.

9. A design system comprising:

a module that enables a designer to specify a boundary between a hard real-time (HRT) portion and a soft real-time (SRT) portion of a system under design and that determines a set of parameters for a buffer for the boundary in response to a set of time constraints associated with the HRT portion, wherein the set of parameters is used to design the system; and

a time-script module that generates a time-script that specifies a set of parameters for a set of behaviors of the HRT portion.

10. The design system of claim 9, wherein the module enables the designer to specify a boundary between a front-end and a back-end in an instrument.

11. The design system of claim 9, wherein the module enables the designer to specify a boundary between a set of channels in a front-end of an instrument.

12. The design system of claim 9, wherein the module enables the designer to specify a boundary in a communication mechanism.

13. The design system of claim 9, wherein the parameters include a capacity for the buffer.

14. The design system of claim 9, further comprising a time-script module that generates a time-script that specifies a set of parameters for a set of behaviors of the HRT portion.

15. The design system of claim 9, wherein the module enables alterations to the boundary at run-time.

16. The design system of claim 9, further comprising a simulator for simulating an operation of the buffer in response to the time constraints.

17. The design system of claim 9, further comprising a partition module for allocating a set of tasks of an application program across the boundary.