Memory device with delayed issuance of internal write command
First Claim
1. A memory device comprising:
- a memory core including an array of memory cells;
a first circuit to receive a write command from external control lines, wherein the write command specifies a write operation;
a second circuit coupled to the first circuit, the second circuit to store the write command for a first time period after the write command is received at the first circuit, wherein the write command initiates a write operation after the first time period has transpired; and
a third circuit to receive data from external data lines after a second time period transpires from when the write command is received at the first circuit, wherein the data is stored in the memory core in response to the write command.
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Abstract
A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device'"'"'s memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.
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Citations
29 Claims
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1. A memory device comprising:
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a memory core including an array of memory cells; a first circuit to receive a write command from external control lines, wherein the write command specifies a write operation; a second circuit coupled to the first circuit, the second circuit to store the write command for a first time period after the write command is received at the first circuit, wherein the write command initiates a write operation after the first time period has transpired; and a third circuit to receive data from external data lines after a second time period transpires from when the write command is received at the first circuit, wherein the data is stored in the memory core in response to the write command. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory device comprising:
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a memory core including an array of dynamic random access memory cells; a transport block to receive a write command from external control lines, wherein the write command specifies a write operation; a write control buffer coupled to the transport block, the write control buffer to store the write command for a first time period after the write command is received at the transport block, wherein the write command initiates the write operation after the first time period has transpired; and a data buffer to receive data from external data lines after a second time period transpires from when the write command is received at the transport block, wherein the data is stored in the memory core in response to the write command. - View Dependent Claims (9, 10)
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11. A memory device comprising:
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a memory core including an array of memory cells; a first circuit to receive a write command from external control lines, wherein the write command specifies a write operation; a second circuit coupled to the first circuit, the second circuit to store the write command for a first time period after the write command is received at the first circuit, wherein the write command initiates a write operation after the first time period has transpired; a third circuit to receive data from external data lines, wherein the data is stored in the memory core in response to the write command; and a fourth circuit to receive mask information from external mask lines, the mask information indicating whether to mask portions of the data to be stored in the memory core. - View Dependent Claims (12, 13, 14)
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15. A memory device comprising:
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a memory core including an array of dynamic random access memory cells; a transport block to receive a write command from external control lines, wherein the write command specifies a write operation; a write control buffer coupled to the transport block, the write control buffer to store the write command for a first time period after the write command is received at the transport block, wherein the write command initiates the write operation after the first time period has transpired; a data buffer to receive data from external data lines, wherein the data is stored in the memory core in response to the write command; and a write mask buffer to receive mask information from external mask lines, the mask information indicating whether to mask portions of the data to be stored in the memory core. - View Dependent Claims (16, 17, 18)
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19. A method of operation in a single chip memory device, the method comprising:
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receiving a write command from control signal lines that are external to the memory device, wherein the write command specifies a write operation; storing the write command for a first time period after receiving the write command; receiving, after a second time period has transpired from receiving the write command, data from data signal lines that are external to the memory device; after the first time period, initiating the write operation in response to the write command; and writing the data to a memory core of the memory device during the write operation. - View Dependent Claims (20, 21, 22, 23, 24)
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25. A method of operating a memory device having a memory core, the method comprising:
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providing a write command that specifies a write operation to the memory device, wherein, after receiving the write command the memory device stores the write command for a first time period before initiating the write operation in response to the write command; providing data to the memory device after a second time period has transpired after providing the write command, wherein the memory device stores the data in the memory core during the write operation. - View Dependent Claims (26, 27, 28, 29)
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Specification