Low power mode for device power management
First Claim
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1. An information handling system having a low power mode, said system comprising:
- information handling equipment having at least one system low power mode;
at least one peripheral device coupled to said information handling equipment having low power mode capability;
a low power enable bit integral to said at least one peripheral device, wherein, when the low power enable bit is in a first logic state, said at least one peripheral device draws reduced power when said information handling equipment is in the at least one system low power mode; and
a non-volatile memory in said information handling equipment, said non-volatile memory having a low power mode bit that is set when the information handling system is currently in a low power mode;
a BIOS memory that includes software for setting the low power enable bit of the at least one peripheral device to a first logic level and thereby causing the at least one peripheral device to draw reduced power in response to the low power mode bit of the non-volatile memory being at a first logic level.
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Abstract
An information handling system having PCI devices which comply with the Power Management Interface Specification have a low power mode that may be used to put Power Management Capability devices into a low power state when the information handling system enters into S4 or S5. A firmware or software low power mode program, retained in non-volatile memory of the information handling system, recognizes when the information handling system is entering S4 or S5. The low power mode program may clear the Power Management Event Enable or not in each of the Power Management Capable devices when the information handling system enters into S4 or S5.
79 Citations
12 Claims
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1. An information handling system having a low power mode, said system comprising:
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information handling equipment having at least one system low power mode; at least one peripheral device coupled to said information handling equipment having low power mode capability; a low power enable bit integral to said at least one peripheral device, wherein, when the low power enable bit is in a first logic state, said at least one peripheral device draws reduced power when said information handling equipment is in the at least one system low power mode; and a non-volatile memory in said information handling equipment, said non-volatile memory having a low power mode bit that is set when the information handling system is currently in a low power mode; a BIOS memory that includes software for setting the low power enable bit of the at least one peripheral device to a first logic level and thereby causing the at least one peripheral device to draw reduced power in response to the low power mode bit of the non-volatile memory being at a first logic level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification