Soft errors handling in EEPROM devices

• US 7,437,631 B2
• Filed: 08/13/2004
• Issued: 10/14/2008
• Est. Priority Date: 05/20/1992
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Mangan, John S., Mehrotra, Sanjay, Guterman, Daniel C., Craig, Jeffrey, Norman, Robert D., Auclair, Daniel L.
• Primary Examiner(s): Kerveros; James C
• Application Number:
  US10/917,870
• Publication Number:
  US 20050058008A1
• Time in Patent Office: 1,523 Days
• Field of Search: 714/721, 365/185.03
• US Class Current: 714/721
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Claims

1. A method of improving data retention in a nonvolatile writable memory having a first reference level and a second reference level, the nonvolatile writable memory having a plurality of memory cells, each of the memory cells being in an first state when storing a charge below the first reference level, and each of the memory cells being in a second state when storing a charge above the second reference level, the method comprising:

writing into each of a set of the plurality of memory cells a respective data value, wherein the respective data values are one of the first and second states;

identifying a memory cell of the set having a charge above the first reference level and below the second reference level; and

rewriting the respective data value into the memory cell.

2. The memory of claim 1, further having a third reference level intermediate between the first and second reference levels, wherein the identifying comprises identifying a memory cell of the set having a charge above the third reference level and below the second reference level.

3. The memory of claim 2, further having a fourth reference level intermediate between the second and third reference levels, wherein the identifying comprises identifying a memory cell of the set having a charge above the third reference level and below the fourth reference level.

4. The memory of claim 1, wherein the rewriting comprises determining the respective data value to rewrite into the data cell using error correction code.

5. A method of improving data retention in a nonvolatile writable memory having a first reference level and a second reference level, the nonvolatile writable memory having a plurality of memory cells organized into sectors, each of the memory cells being in an first state when storing a charge below the first reference level, and each of the memory cells being in a second state when storing a charge above the second reference level, the method comprising:

accessing a first sector of said memory cells each storing a respective data value, wherein the respective data values are one of the first and second states;

identifying a second sector of said memory cells having one or more memory cells with a charge above the first reference level and below the second reference level; and

rewriting the respective data values stored in the memory cells of the second sector.

6. The memory of claim 5, wherein said accessing a first sector of said memory cells comprises programming data values into said memory cells of the first sector, wherein the data values are one of the first and second states.

7. The memory of claim 5, wherein said accessing a first sector of said memory cells comprises reading the data values stored in said memory cells of the first sector, wherein the data values are one of the first and second states.

8. The memory of claim 5, wherein said second sector is chosen at random prior to said identifying.

9. The memory of claim 5, wherein a memory cells of said first sector shares a common bit line with a memory cell of said second sector.