Fault diagnosis of compressed test responses having one or more unknown states

• US 7,437,640 B2
• Filed: 08/25/2005
• Issued: 10/14/2008
• Est. Priority Date: 02/13/2003
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Wang, Chen, Mrugalski, Grzegorz, Tyszer, Jerzy, Pogiel, Artur, Rajski, Janusz
• Primary Examiner(s): Ton; David
• Application Number:
  US11/213,672
• Publication Number:
  US 20060041814A1
• Time in Patent Office: 1,146 Days
• Field of Search: 714/732, 714/726, 714/733, 714/729, 714/727, 726/12
• US Class Current: 714/729
• CPC Class Codes: G01R 31/28 Testing of electronic circuits, e.g. by signal tracer EMC, EMP or similar testing of electronic circuits G01R31/002; testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers or computer components G06F11/00; checking static stores for correct operation G11C29/00 ; testing receivers or transmitters of transmission systems H04B17/00
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G01R 31/318583 Design for test
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, a compactor for compacting test responses in a circuit-under-test is disclosed. In this embodiment, the compactor includes an injector network comprising combinational logic and includes injector-network outputs and injector-network inputs. At least some of the injector-network inputs are logically coupled to two or more injector-network outputs according to respective injector polynomials. The exemplary compactor further comprises a selection circuit that includes selection-circuit outputs coupled to the injector-network inputs and selection-circuit inputs coupled to scan-chain outputs of the circuit-under-test. The selection circuit is configured to selectively route signals from the scan-chain outputs to the injector-network inputs according to one of plural different input configurations.

Claims

1. A compactor for compacting test responses in a circuit-under-test, comprising:

an injector network comprising combinational logic, the injector network further comprising injector-network outputs and injector-network inputs, at least some of the injector-network inputs being logically coupled to two or more injector-network outputs according to respective injector polynomials; and

a selection circuit comprising selection-circuit outputs coupled to the injector-network inputs and selection-circuit inputs coupled to scan-chain outputs of the circuit-under-test, the selection circuit being configured to selectively route signals from the scan-chain outputs to the injector-network inputs according to one of plural different input configurations.

2. The compactor of claim 1, wherein the selection circuit is configured to alternate input configurations in response to a control signal.

3. The compactor of claim 2, wherein the multiple different input configurations comprise two input configurations, and wherein the control signal comprises a single-bit control signal.

4. The compactor of claim 1, wherein scan-chain outputs of the circuit-under-test are clocked out at a first rate and wherein the selection circuit is configured to alternate input configurations at a rate faster than the first rate at which the scan-chain outputs are clocked.

5. The compactor of claim 1, further comprising a plurality of memory elements coupled to the injector-network outputs.

6. The compactor of claim 5, wherein the respective injector polynomials are selected to prevent masking of an unknown value in the memory elements.

7. The compactor of claim 1, wherein the plurality of memory elements comprises a first register, the circuit further comprising a second register also coupled to the injector-network outputs, the first and the second registers being coupled to the injector-network outputs via one or more demultiplexers.

8. The compactor of claim 7, wherein the demultiplexers are configured to selectively route values from the injector-network outputs to one of the first register or the second register in response to a control signal;

and

wherein the selection circuit is configured to alternate input configurations in response to the control signal.

9. One or more tangible computer-readable media storing computer-executable instructions for causing a computer system to design the circuit of claim 1.

10. One or more tangible computer-readable media storing design data for implementing or simulating the apparatus of claim 1.

11. A circuit, comprising:

a circuit-under-test that is part of the circuit, the circuit-under-test comprising scan chains; and

a compactor circuit coupled to the scan chains and configured to receive a test response output from the scan chains, the compactor circuit being operable to generate two or more compressed test responses from the test response, the two or more compressed test responses being generated according to different compaction functions, the compactor circuit also comprising at least one memory element.

12. The circuit of claim 11, wherein the compactor circuit further comprises an injector network of XOR or XNOR gates and wherein the at least one memory element of the compactor circuit is part of at least one register coupled to outputs of the injector network.

13. The circuit of claim 11, wherein the compactor circuit further comprises a single injector network operable to generate the two or more compressed test responses.

14. The circuit of claim 13, wherein the compactor circuit further comprises one or more switches coupled between outputs of the scan chains and inputs of the single injector network, the one or more switches being configured to selectively couple outputs of the scan chains to the inputs of the single injector network according to two or more different input configurations.

15. The circuit of claim 14, wherein the compactor circuit is feedback-free.

16. One or more tangible computer-readable media storing computer-executable instructions for causing a computer system to design the circuit of claim 11.

17. One or more tangible computer-readable media storing design data for implementing or simulating the circuit of claim 11.

18. A method of synthesizing a compactor, comprising:

generating one or more polynomials representing possible injector networks for coupling a plurality of memory elements in the compactor to respective scan-chain outputs; and

the polynomials being generated so that the number of memory elements between connections to the respective scan-chain outputs in a register of the compactor is greater than a minimum value and less than a maximum value, the minimum value being greater than one and the maximum value being less than the total number of memory elements in the register.

19. The method of claim 18, further comprising selecting one of the polynomials for a respective scan-chain output, the selection being based at least in part on the number of scan-chain outputs to which the memory elements associated with the selected polynomial are already assigned.

20. The method of claim 19, wherein the selection is performed so that the memory elements of the compactor are each coupled to approximately the same number of scan-chain outputs.

21. The method of claim 18, wherein the polynomial selected is a first polynomial, the method further comprising selecting a second polynomial for another respective scan-chain output, the second polynomial being a nonshifted version of the first polynomial.

22. One or more tangible computer-readable media storing computer-executable instructions for causing a computer system to perform the method of claim 18.

23. One or more tangible computer-readable media storing circuit design data for implementing or simulating a compactor synthesized by the method of claim 18.

24. A circuit containing a compactor synthesized according to the method of claim 18.