Memory debugger for system-on-a-chip designs

• US 7,437,692 B2
• Filed: 11/10/2003
• Issued: 10/14/2008
• Est. Priority Date: 11/10/2003
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Oberlaender, Klaus J.
• Primary Examiner(s): Do; Thuan
• Application Number:
  US10/705,101
• Publication Number:
  US 20050102572A1
• Time in Patent Office: 1,800 Days
• Field of Search: 716/1, 716/4, 716/18, 716/19
• US Class Current: 716/138
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A simulation/debugging method for SOC designs that utilizes initial memory values loaded into a simulation model. A test program is then executed, and incremetal transaction records are generated for each incremental memory access (e.g., data write operations). Each transaction record includes a timestamp, address and data values. The transaction record information is stored/captured on a high level-based (i.e., system address-based) domain that takes into account all the tiling, interleaving, scrambling, and unaligned accessing used in the simulated SOC design, rather than on a low level-based (i.e., physical memory address-based) domain. Upon completing the simulation, the instantaneous memory contents at any selected point in time during the simulated execution are calculated by combining the initial data and intermediate transaction record information. Automatic memory dump and sanity check tests verify the integrity of the final data value and incremental transactions. Cache memory information is collected and displayed using a system-level format.

Claims

1. A method for debugging a system-on-chip (SOC) integrated circuit design including a processor core and a memory array for storing data generated by the processor core, the SOC integrated circuit design being represented by a simulation model, the method comprising:

loading initial data values into the memory array associated with the simulation model and simulating the execution of a predefined test program using the initial data values;

during the simulated execution, generating a plurality of transaction records identifying write operations during which updated data values are written into the memory array, wherein each transaction record includes an associated timestamp, associated address information, and the updated data values written during the associated write operation; and

upon completing the simulated execution, determining instantaneous data values stored in the memory array at a selected point in time during the simulated execution by combining the initial data values and updated data values from one or more transaction records.

2. The method according to claim 1, wherein loading the initial data values comprises:

converting system-level address/data information to physical-level address/data information based on the SOC integrated circuit design;

generating a transmission stream including the physical-level address/data information; and

writing the transmission stream into the memory array of the simulation model.

3. The method according to claim 2, wherein writing the transmission stream occurs before simulating the execution of the predefined test program.

4. The method according to claim 1, wherein generating a plurality of transaction records comprises monitoring an interface circuit of the memory array, and generating said each transaction record when said associated address information and said updated data values are detected in the interface circuit.

5. The method according to claim 4, wherein generating said each transaction record comprises capturing a timestamp from a system clock upon detecting said associated address information and said updated data values in the interface circuit.

6. The method according to claim 4, wherein generating said each transaction record comprises converting said associated address information from a physical-level format to a system-level format.

7. The method according to claim 4, wherein generating said each transaction record comprises capturing at least one of an access width and an access type associated with the updated data values.

8. The method according to claim 4, further comprising storing said transaction record in an expanded format that identifies each byte location of the memory array that is accessed during said associated write operation.

9. The method according to claim 4, wherein each transaction record further comprises at least one of a transaction source identifier and a program counter value.

10. The method according to claim 1,

wherein the SOC integrated circuit design includes a first-in first-out (fifo) memory device for storing a plurality of fifo data values,

wherein generating the plurality of transaction records includes generating a first transaction record identifying a push write operation occurring at a first point in time during which a first fifo data value is written into the fifo memory device, and

wherein determining instantaneous data values stored in the fifo memory device at the first selected point in time includes identifying the push write operation from the first transaction record, and calculating changes to each of the plurality of fifo data values in response to writing the first fifo data value into the fifo memory device.

11. The method according to claim 10, further comprising detecting an overflow condition of the fifo memory device by determining an instantaneous number of data values stored in the fifo memory device at the first selected point in time, and comparing the instantaneous number with a predetermined maximum number.

12. The method according to claim 1,

wherein the SOC integrated circuit design includes a first-in first-out (fifo) memory device for storing a plurality of fifo data values,

wherein generating the plurality of transaction records includes generating a first transaction record identifying a pop operation occurring at a first point in time during which a first fifo data value is read from the fifo memory device, and

wherein determining instantaneous data values stored in the fifo memory device at the first selected point in time includes identifying the pop operation from the first transaction record, and calculating changes to each of the plurality of fifo data values in response to reading the first fifo data value from the fifo memory device.

13. The method according to claim 12, further comprising detecting an underflow condition of the fifo memory device by determining an instantaneous number of data values stored in the fifo memory device, and detecting execution of the pop operation when the instantaneous number is zero.

14. The method according to claim 1, wherein determining an instantaneous data value stored at a selected memory location of the memory array at the selected time comprises identifying a group of transaction records having timestamp values between a start time of the simulated execution and said selected time and that include updated data values written into the selected memory location, and modifying the instantaneous data value using a most-recent transaction record from the group of transaction records having the highest timestamp value.

15. The method according to claim 1, further comprising generating a graphical display on an output device that simultaneously displays both the instantaneous data values stored in the memory array, and at least one of said transaction records.

16. The method according to claim 1, further comprising:

combining the initial data values with said updated data values from all of said transaction records to generate a final memory image; and

comparing the final memory image with a known good memory image and flagging differences.

17. The method according to claim 1, further comprising:

combining the initial data values with said updated data values from all of said transaction records to generate a final memory image;

converting the final memory image into a final memory signature value; and

comparing the final memory signature with a known good signature.

18. The method according to claim 1, further comprising:

generating a plurality of second transaction records identifying read operations during which selected second data values are read from the memory array, wherein each transaction record includes an associated timestamp, associated address information, and the selected second data values accessed during the associated read operation; and

verifying the selected second data values for each associated address by comparing the selected second data values with the instantaneous data values previously determined for the associated address.

19. The method according to claim 18, further comprising detecting access to an uninitiated memory cell, and generating an associated warning flag.

20. The method according to claim 1,

wherein the memory array comprises cache memory for storing a plurality of cache data values, the cache memory including a tag array, wherein generating the plurality of transaction records includes generating a first transaction record identifying a cache write operation occurring at a first point in time during which a first cache data value is written into the cache memory and a corresponding change is generated in the tag array, where the first transaction record includes a tag field identifying the change to the tag array, and

wherein determining instantaneous data values stored in the cache memory at the first selected point in time includes identifying the cache write operation from the first transaction record, and calculating the change to the tag array based on information stored in the tag field of the first transaction record.

21. The method according to claim 1, wherein the updated data values contain only incremental data changes associated with the one or more transaction records.

22. A computer-usable medium storing computer-executable instructions which when executed perform a process of simulating and analyzing a system-on-chip (SOC) integrated circuit design, the SOC integrated circuit design including a processor core and a memory array for storing data generated by the processor core, the SOC integrated circuit design being represented by a simulation model, the process comprising:

loading initial data values into the memory array associated with the simulation model and simulating the execution of a predefined test program using the initial data values;

during the simulated execution, generating a plurality of transaction records identifying write operations during which updated data values are written into the memory array, wherein each transaction record includes an associated timestamp, associated address information, and the updated data values written during the associated write operation; and

determining instantaneous data values stored in the memory array at a selected time during the simulation process by combining the initial data values and updated data values from one or more transaction records.

23. The computer-usable medium according to claim 22, wherein loading the initial data values comprises:

converting system-level address/data information to physical-level address/data information based on the SOC integrated circuit design;

generating a transmission stream including the physical-level address/data information; and

writing the transmission stream into the memory array of the simulation model.

24. The computer-usable medium according to claim 22, wherein the process further comprises:

generating a plurality of second transaction records identifying read operations during which selected second data values are read from the memory array, wherein each transaction record includes an associated timestamp, associated address information, and the selected second data values accessed during the associated read operation; and

verifying the selected second data values for each associated address by comparing the selected second data values with the instantaneous data values previously determined for the associated address.

25. The computer-usable medium according to claim 22, wherein the updated data values contain only incremental data changes associated with the one or more transaction records.

26. A system for debugging a system-on-chip (SOC) integrated circuit design including a processor core and a memory array configured to store data generated by the processor core, the system including storage configured to store a simulation model representative of the SOC integrated circuit design, the simulation model including a processor core and a memory array configured to store data generated by the processor core, the system also including and unit configured to perform a debugging process comprising:

loading initial data values into the memory array associated with the simulation model and simulating the execution of a predefined test program using the initial data values;

during the simulated execution, generating a plurality of transaction records identifying write operations during which updated data values are written into the memory array, wherein each transaction record includes an associated timestamp, associated address information, and the updated data values written during the associated write operation; and

determining instantaneous data values stored in the memory array at a selected time during the simulation process by combining the initial data values and updated data values from one or more transaction records.

27. The system according to claim 26, wherein loading the initial data values comprises:

converting system-level address/data information to physical-level address/data information based on the SOC integrated circuit design;

generating a transmission stream including the physical-level address/data information; and

writing the transmission stream into the memory array of the simulation model.

28. The system according to claim 26, wherein the updated data values contain only incremental data changes associated with the one or more transaction records.