Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices

• US 7,437,695 B1
• Filed: 04/05/2005
• Issued: 10/14/2008
• Est. Priority Date: 03/03/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Ranjan, Abhishek, Knol, David A., Raje, Salil R.
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Levin; Naum B
• Application Number:
  US11/100,290
• Time in Patent Office: 1,288 Days
• Field of Search: 716 4- 6, 703/19
• US Class Current: 716/113
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method of performing timing analysis on a circuit design for an integrated circuit (IC) can include selecting a physical portion of the IC that includes at least one instance of a logic hierarchy and generating a local timing constraint specific to the physical portion. The method also can include creating a software representation of the physical portion of the IC. The software representation can specify the local timing constraint and a shell netlist for the physical portion. The method further can include performing a timing analysis upon, at least part of, the circuit design using the software representation.

Claims

1. A method of performing timing analysis on a circuit design for an integrated circuit (IC) comprising:

selecting a physical block of the circuit design, wherein the physical block includes at least one instance of a logic hierarchy;

generating a local timing constraint specific to the physical block, wherein the local timing constraint is a function of a pre-routing estimate of a global timing constraint involving the physical block,

wherein the local timing constraint specifies a portion of the global timing constraint corresponding to a portion of a signal path covered by the global timing constraint, wherein the portion of the signal path is defined by a first endpoint that is a top level port of the physical block and a second endpoint that is a first encountered circuit element, on the signal path within the physical block, comprising memory;

creating a software representation of the physical block, wherein the software representation specifies the local timing constraint and a shell netlist for the physical block,

wherein the shell netlist specifies top level ports of the physical block and elements disposed in signal paths extending from each of the top level ports of the physical block up to, and including, a first encountered circuit element comprising memory within the physical block; and

performing a timing analysis upon, at least part of, the circuit design using the software representation.

2. The method of claim 1, said generating step further comprising modifying a global timing constraint of the circuit design thereby resulting in the local timing constraint, wherein the local timing constraint pertains only to the physical block.

3. The method of claim 1, said generating step further comprising determining the local timing constraint by multiplying the global timing constraint by a factor determined from a ratio of a delay of the portion of the signal path to a delay of the signal path.

4. The method of claim 3, wherein the global timing constraint is associated with a defined signal path, said determining step further comprising calculating the part of the global timing constraint attributable to the physical block using a function that depends, at least in part, upon a delay estimate of the defined signal path and a delay estimate of a part of the defined signal path involving the physical block.

5. The method of claim 1, wherein the local timing constraint is not derived from a global timing constraint and pertains only to the physical block.

6. The method of claim 1, wherein the software representation includes delays of nets specified in the shell netlist.

7. A method of performing timing analysis on a circuit design for an integrated circuit (IC) comprising:

generating at least one local timing constraint for a data structure representing a physical area of at least part of the circuit design on the IC, wherein the local timing constraint is a function of a pre-routing estimate of a global timing constraint involving the physical area of at least part of the circuit design on the IC,

wherein the local timing constraint specifies a portion of the global timing constraint corresponding to a portion of a signal path covered by the global timing constraint, wherein the portion of the signal path is defined by a first endpoint that is a top level port of the physical block and a second endpoint that is a first encountered circuit element, on the signal path within the physical block, comprising memory;

determining a shell netlist for the data structure,

wherein the shell netlist specifies top level ports of the data structure, nets, and combinational logic extending from each top level port up to, and including, a first encountered circuit element comprising memory within the data structure;

defining a software-based model of the data structure;

associating the shell netlist and the at least one local timing constraint with the software-based model; and

replacing a netlist for the data structure with the software-based model when estimating timing information for at least a portion of the circuit design.

8. The method of claim 7, wherein the software-based model specifies a physical area of the IC and logical attributes.

9. The method of claim 7, said generating step further comprising determining the local timing constraint by multiplying the global timing constraint by a factor determined from a ratio of a delay of the portion of the signal path to a delay of the signal path.

10. The method of claim 7, wherein the local timing constraint is not derived from a global timing constraint and pertains only to the data structure.