Substrate driven field-effect transistor

• US 7,439,556 B2
• Filed: 03/29/2005
• Issued: 10/21/2008
• Est. Priority Date: 03/29/2005
• Status: Active Grant

• Current Assignee: Flextronics International USA Incorporated (Flex, Ltd.)
• Original Assignee: ColdWatt, Inc. (Flex, Ltd.)
• Inventors: Brar, Berinder P. S., Asbeck, Peter M.
• Primary Examiner(s): Dickey; Thomas L
• Application Number:
  US11/093,592
• Publication Number:
  US 20060226477A1
• Time in Patent Office: 1,302 Days
• Field of Search: 257/192, 257/194
• US Class Current: 257/194
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A substrate driven field effect transistor (FET) and a method of forming the same. In one embodiment, the substrate driven FET includes a substrate having a source contact covering a substantial portion of a bottom surface thereof and a lateral channel above the substrate. The substrate driven FET also includes a drain contact above the lateral channel. The substrate driven FET still further includes a source interconnect that connects the lateral channel to the substrate operable to provide a low resistance coupling between the source contact and the lateral channel.

Claims

1. A substrate driven field effect transistor (FET), comprising:

a conductive substrate having a source contact covering a substantial portion of a bottom surface thereof;

a first buffer layer above and formed from a similar material to said conductive substrate;

an isolation layer above said first buffer layer;

a second buffer layer above said isolation layer;

a lateral channel above said second buffer layer and formed from a similar material to said conductive substrate;

a drain contact above said lateral channel and formed on a top surface of said substrate driven FET; and

a source interconnect formed through said lateral channel to, without penetrating through, said conductive substrate operable to provide a low resistance coupling between said source contact and said lateral channel.

2. The substrate driven FET as recited in claim 1 wherein said first buffer layer is an n+ epitaxial buffer layer.

3. The substrate driven FET as recited in claim 1 wherein said isolation layer is oppositely doped from said conductive substrate.

4. The substrate driven FET as recited in claim 1 wherein said lateral channel is pseudomorphic.

5. The substrate driven FET as recited in claim 1 further comprising a barrier region interposed between said lateral channel and said drain contact.

6. The substrate driven FET as recited in claim 1 further comprising a gate interposed between said lateral channel and said drain contact.

7. The substrate driven FET as recited in claim 1 wherein said source interconnect is formed from a group consisting of:

a trench, and

an implant region.

8. The substrate driven FET as recited in claim 1 further comprising a metal layer on sidewalls of said source interconnect.

9. The substrate driven FET as recited in claim 1 further comprising a drain post interposed between said lateral channel and said drain contact.

10. The substrate driven FET as recited in claim 1 further comprising a dielectric layer interposed between said lateral channel and said drain contact.

11. A method of forming a substrate driven field effect transistor (FET) on a conductive substrate, comprising:

forming a first buffer layer with a similar material to and over said conductive substrate;

forming an isolation layer over said first buffer layer;

forming a second buffer over said isolation layer;

forming a lateral channel with a similar material to said conductive substrate over said second buffer layer;

forming a source interconnect through said lateral channel to, without penetrating through, said conductive substrate;

forming a drain contact above said lateral channel on a top surface of said substrate driven FET; and

forming a source contact over a substantial portion of a bottom surface of said conductive substrate, said source interconnect operable to provide a low resistance coupling between said source contact and said lateral channel.

12. The method as recited in claim 11 wherein said first buffer layer is an n+ epitaxial buffer layer.

13. The method as recited in claim 11 wherein said isolation layer is oppositely doped from said conductive substrate.

14. The method as recited in claim 11 wherein said lateral channel is pseudomorphic.

15. The method as recited in claim 11 further comprising forming a barrier region over said lateral channel.

16. The method as recited in claim 11 further comprising forming a gate over said lateral channel.

17. The method as recited in claim 11 wherein said source interconnect is formed from a group consisting of:

a trench, and

an implant region.

18. The method as recited in claim 11 further comprising forming a metal layer on sidewalls of said source interconnect.

19. The method as recited in claim 11 further comprising forming a drain post over said lateral channel.

20. The method as recited in claim 11 further comprising forming a dielectric layer over said lateral channel.