Semiconductor device having a lateral channel and contacts on opposing surfaces thereof

• US 7,439,557 B2
• Filed: 03/29/2005
• Issued: 10/21/2008
• Est. Priority Date: 03/29/2005
• Status: Active Grant

• Current Assignee: Flextronics International USA Incorporated (Flex, Ltd.)
• Original Assignee: ColdWatt, Inc. (Flex, Ltd.)
• Inventors: Ha, Wonill, Brar, Berinder P. S.
• Primary Examiner(s): Dickey; Thomas L
• Application Number:
  US11/094,632
• Publication Number:
  US 20060226478A1
• Time in Patent Office: 1,302 Days
• Field of Search: 257/192, 257/194
• US Class Current: 257/194
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7785 with more than one donor layer

Abstract

A semiconductor device having a lateral channel with contacts on opposing surfaces thereof and a method of forming the same. In one embodiment, the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof. The semiconductor device also includes a lateral channel above the conductive substrate. The semiconductor device further includes a second contact above the lateral channel. The semiconductor device still further includes an interconnect that connects the lateral channel to the conductive substrate. The interconnect is operable to provide a low resistance coupling between the first contact and the lateral channel.

Claims

1. A semiconductor device, comprising:

a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof;

an isolation layer oppositely doped from and above said conductive substrate;

a lateral channel above said isolation layer;

a second contact above said lateral channel; and

an interconnect formed through said lateral channel to, without penetrating through, said conductive substrate operable to provide a low resistance coupling between said first contact and said lateral channel.

2. The semiconductor device as recited in claim 1 further comprising a buffer layer interposed between said conductive substrate and said isolation layer.

3. The semiconductor device as recited in claim 1 further comprising a spacer layer interposed between said isolation layer and said lateral channel.

4. The semiconductor device as recited in claim 1 further comprising a barrier layer interposed between said isolation layer and said lateral channel.

5. The semiconductor device as recited in claim 1 further comprising a barrier layer interposed between said lateral channel and said second contact.

6. The semiconductor device as recited in claim 1 further comprising a modulation doped spacer layer interposed between said lateral channel and said second contact.

7. The semiconductor device as recited in claim 1 further comprising a recess layer interposed between said lateral channel and said second contact.

8. The semiconductor device as recited in claim 1 further comprising an etch-stop layer interposed between said lateral channel and said second contact.

9. The semiconductor device as recited in claim 1 further comprising first and second source/drain contact layers interposed between said lateral channel and said second contact.

10. The semiconductor device as recited in claim 1 further comprising a gate located in a gate recess interposed between said lateral channel and said second contact.

11. The semiconductor device as recited in claim 1 further comprising a dielectric layer interposed between said lateral channel and said second contact.

12. The semiconductor device as recited in claim 1 further comprising a drain post interposed between said lateral channel and said second contact.

13. The semiconductor device as recited in claim 1 wherein said conductive substrate is formed from gallium arsenide.

14. The semiconductor device as recited in claim 1 further comprising a barrier layer interposed between said conductive substrate and said second contact configured at least in part to form an intrinsic body diode with said isolation layer within said semiconductor device.

15. The semiconductor device as recited in claim 1 further comprising a buffer layer formed of an alternating aluminum-gallium arsenide/gallium arsenide (“

AlGaAs/GaAs”

) super-lattice buffer interposed between said isolation layer and said lateral channel.

16. The semiconductor device as recited in claim 1 further comprising a modulation doped barrier layer formed from aluminum gallium-arsenide (“

AlGaAs”

) interposed between said isolation layer and said lateral channel.

17. The semiconductor device as recited in claim 1 further comprising a buffer layer and a barrier layer interposed between said conductive substrate and said lateral channel configured to form at least in part back-to-back diodes with said isolation layer within said semiconductor device.

18. The semiconductor device as recited in claim 1 wherein said lateral channel is formed from indium gallium arsenide.

19. The semiconductor device as recited in claim 1 wherein said lateral channel is pseudomorphic.

20. The semiconductor device as recited in claim 1 wherein said interconnect is located in a via formed through said semiconductor device down to said conductive substrate.

21. The semiconductor device as recited in claim 1 wherein said interconnect has a metal layer on horizontal and semi-horizontal surfaces thereof and is plated with a metal material.

22. The semiconductor device as recited in claim 1 wherein said semiconductor device is a depletion mode device.

23. The semiconductor device as recited in claim 1 wherein said semiconductor device is an enhancement mode device.

24. The semiconductor device as recited in claim 1 further comprising a gate located in a gate recess located in said semiconductor device proximate said lateral channel thereby providing an enhancement mode device.

25. A semiconductor device, comprising:

a substrate having a source contact covering a substantial portion of a bottom surface thereof;

a first buffer layer formed over said substrate;

an isolation layer oppositely doped from and formed over said first buffer layer;

a first spacer layer formed over said isolation layer;

a second buffer layer formed over said first spacer layer;

a first barrier layer formed over said second buffer layer;

a second spacer layer formed over said first barrier layer;

a lateral channel formed over said second spacer layer;

a third spacer layer formed over said lateral channel;

a second barrier layer formed over said third spacer layer;

a recess layer formed over said second barrier layer;

an etch-stop layer formed over said recess layer;

first and second source/drain contact layers formed over said etch-stop layer;

a source interconnect formed through said lateral channel to, without penetrating through, said substrate operable to provide a low resistance coupling between said source contact and said lateral channel;

a gate located in a gate recess formed though said first and second source/drain contact layers, said etch-stop and said recess layer;

a dielectric layer formed over said gate, and said first and second source/drain contact layers;

a drain post located in a drain via formed through said dielectric layer and over said first and second source/drain contact layers; and

a drain contact coupled to said drain post.

26. The semiconductor device as recited in claim 25 wherein said substrate is formed from gallium arsenide.

27. The semiconductor device as recited in claim 25 wherein said isolation layer forms an intrinsic body diode at least in part with said first barrier layer.

28. The semiconductor device as recited in claim 25 wherein said second buffer layer is an alternating aluminum-gallium arsenide/gallium arsenide (“

AlGaAs/GaAs”

) super-lattice buffer.

29. The semiconductor device as recited in claim 25 wherein said first barrier layer is formed from aluminum gallium-arsenide (“

AlGaAs”

).

30. The semiconductor device as recited in claim 25 wherein said first barrier layer is modulation doped.

31. The semiconductor device as recited in claim 25 wherein said isolation layer forms back-to-back diodes at least in part with said first buffer layer and said first barrier layer.

32. The semiconductor device as recited in claim 25 wherein said lateral channel is formed from indium gallium arsenide.

33. The semiconductor device as recited in claim 25 wherein said lateral channel is pseudomorphic.

34. The semiconductor device as recited in claim 25 wherein said third spacer layer is modulation doped.

35. The semiconductor device as recited in claim 25 wherein said source interconnect is located in a source via formed through said semiconductor device down to said substrate.

36. The semiconductor device as recited in claim 25 wherein said source interconnect has a metal layer on horizontal and semi-horizontal surfaces thereof.

37. The semiconductor device as recited in claim 25 wherein said source interconnect is plated with a metal material.

38. The semiconductor device as recited in claim 25 wherein said gate is formed by multiple layers.

39. The semiconductor device as recited in claim 25 wherein said drain post is plated with a metal material.

40. The semiconductor device as recited in claim 25 wherein said source and drain contacts are formed by a metallic alloy.

41. The semiconductor device as recited in claim 25 wherein said semiconductor device is a depletion mode device.

42. The semiconductor device as recited in claim 25 wherein said semiconductor device is an enhancement mode device.

43. The semiconductor device as recited in claim 25 wherein said third spacer layer is modulation doped to a selected level to provide an enhancement mode device.

44. The semiconductor device as recited in claim 25 wherein said gate recess is further recessed into said semiconductor device proximate said lateral channel thereby providing an enhancement mode device.