Liquid crystal display device and fabricating method thereof

• US 7,439,586 B2
• Filed: 06/03/2005
• Issued: 10/21/2008
• Est. Priority Date: 06/05/2004
• Status: Expired due to Fees

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kwack, Hee Young, Jung, Tae Young, Lee, Ji No
• Primary Examiner(s): Lee; Eugene
• Application Number:
  US11/143,681
• Publication Number:
  US 20050269638A1
• Time in Patent Office: 1,236 Days
• Field of Search: 257/347, 257/59, 257/72, 257/48
• US Class Current: 257/347
• CPC Class Codes: G02F 1/133388 with constructional differences between the display region and the peripheral region
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

A base thin film transistor (TFT) substrate includes a substrate, array areas on the substrate; at least one dummy area on the substrate and between the array areas; an insulating film on the substrate; at least one aperture through the insulating film and arranged within the at least one dummy area; and at least one post arranged within the at least one aperture.

Claims

1. A base thin film transistor (TFT) array substrate, comprising:

a substrate;

a plurality of array areas on the substrate;

at least one dummy area on the substrate and between the plurality of array areas;

an insulating film on the substrate;

at least one aperture through the insulating film and arranged within the at least one dummy area; and

at least one post arranged within the at least one aperture, wherein the at least one aperture includes a plurality of holes.

2. The base TFT array substrate of claim 1, wherein the at least one post comprises insulating material.

3. The base TFT array substrate of claim 2, wherein the at least one post includes:

a gate insulating film; and

a passivation film.

4. The base TFT array substrate of claim 1, further comprising a dummy sealant pattern on the at least one post.

5. The base TFT array substrate of claim 1, further comprising a transparent conductive material formed within the plurality of holes and the aperture.

6. The base TFT array substrate of claim 1, wherein a width of each hole is less than a width of the dummy sealant pattern formable over the at least one aperture.

7. The base TFT array substrate of claim 1, further comprising a plurality of TFTs within each array area.