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Method of fabricating array substrate having color filter on thin film transistor structure

  • US 7,440,041 B2
  • Filed: 10/04/2006
  • Issued: 10/21/2008
  • Est. Priority Date: 12/23/2002
  • Status: Expired due to Fees
First Claim
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1. A method of forming an array substrate device for use in a liquid crystal display device, comprising:

  • forming a gate line on a substrate along a first direction, the gate line including a gate pad at one end thereof;

    forming a first insulating layer on the substrate to cover the gate line;

    forming a data line over the first insulating layer along a second direction perpendicular to the first direction on the substrate, the data line defining a pixel region with the gate line and including a data pad at one end thereof;

    forming a thin film transistor at a crossing region of the gate and data lines, the thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode;

    forming a black matrix overlapping the thin film transistor, the gate line, and the data line except a first portion of the drain electrode;

    forming a second insulating layer over an entire surface of the substrate to cover the black matrix;

    patterning the first and second insulating layers to expose the first portion of drain electrode, to form a gate pad contact hole exposing the gate pad, and to form a data pad contact hole exposing the data pad;

    forming a first transparent electrode layer over an entire surface of the substrate to cover the patterned second insulating layer and contacting the exposed first portion of the drain electrode;

    dropping a liquid-type color resin onto the first transparent electrode layer within the pixel region to form a color filter within the pixel region;

    forming a second transparent electrode layer over an entire surface of the substrate to cover the color filter and the first transparent electrode layer; and

    patterning the first and second transparent electrode layers to form first and second pixel electrodes, a double-layered gate pad terminal, and a double-layered data pad terminal.

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