Semiconductor memory device

• US 7,440,303 B2
• Filed: 03/14/2007
• Issued: 10/21/2008
• Est. Priority Date: 09/14/2004
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Liaw, Corvin
• Primary Examiner(s): Elms; Richard T.
• Assistant Examiner(s): Yang; Han
• Application Number:
  US11/724,057
• Publication Number:
  US 20070211528A1
• Time in Patent Office: 587 Days
• Field of Search: 365/158, 365/171, 365/173, 365/148, 365/163, 365/48, 365/46
• US Class Current: 365/48
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A semiconductor memory device includes resistance memory elements that are coupled to selection transistors addressed by word lines and bit lines. The memory elements are read by read/write lines arranged parallel to the word lines. Two successive memory elements along a read/write line are coupled to selection transistors that are coupled to different word lines.

Claims

1. A semiconductor memory device comprising a matrix-like arrangement of memory elements in rows and columns, the semiconductor memory device comprising:

a plurality of selection transistors, each selection transistor having two source/drain regions and an intervening channel controlled by a gate electrode, the selection transistors being arranged in rows and columns, said rows defined as being parallel to word lines and said columns defined as being parallel to bitlines;

a plurality of word lines, each word line being coupled to the gate electrodes of selection transistors arranged in a row;

a plurality of bit lines, each bit line being coupled to a respective source/drain region of a plurality of selection transistors arranged along said bit line, no two of said pairs arranged in the same row, wherein each selection transistor is coupled to precisely one bit line; and

a plurality of memory elements formed as resistance memory elements, each one of the memory elements being coupled to only one read/write line, and each memory element being further coupled between its respective read/write line and a source/drain region of a selection transistor that is not coupled to a bit line, wherein memory elements in adjacent columns along a read/write line are coupled to selection transistors that are coupled to different word lines.

17. The semiconductor memory device as claimed in claim 1, wherein the memory elements comprise resistance memory elements whose electrical resistance is altered during programming by an applied programming current.

18. The semiconductor memory device as claimed in claim 17, wherein:

the memory elements comprise solid-state ionic memory elements; and

the read/write line forms an electrode of a memory element coupled to that read/write line.

2. A semiconductor memory device comprising a matrix-like arrangement of memory elements in rows and columns, the semiconductor memory device comprising:

a plurality of selection transistors, each selection transistor having two source/drain regions and an intervening channel controlled by a gate electrode, the selection transistors being arranged in rows and columns, said rows parallel to word lines and said columns parallel to bit lines;

a plurality of word lines, each word line being coupled to the gate electrodes of the selection transistors in a respective row;

a plurality of bit lines, each bit line being coupled to a respective source/drain region of a plurality of selection transistors, no two of which are arranged in the same row, wherein each selection transistor is coupled to precisely one bit line; and

a plurality of memory elements formed as resistance memory elements, the memory elements being coupled row by row to read/write lines, each memory element being coupled between a respective read/write line and a source/drain region of a selection transistor that is not coupled to a bit line, wherein two successive memory elements along a read/write line are coupled to selection transistors that are coupled to different word lines wherein;

the totality of the memory elements is divided into groups comprising the same number of memory elements;

no two memory elements of the same group are coupled to the same read/write line;

all the memory elements of the same group are coupled to the same selection transistor;

the totality of the read/write lines are divided into groups, each group comprising as many read/write lines as there are memory elements coupled to a respective selection transistor; and

each group of read/write lines is coupled to groups of memory elements, such that, from all the groups of memory elements of which a memory element is coupled to one read/write line of said group, each memory element is coupled to another read/write line of said group.

3. The semiconductor memory device as claimed in claim 2, wherein a plurality of groups of memory elements are coupled to the same selection transistor.

4. The semiconductor memory device as claimed in claim 2, wherein the memory elements of only one group of memory elements are coupled to each selection transistor.

5. The semiconductor memory device as claimed in claim 4, wherein the read/write lines that are coupled to the memory elements of the same group are coupled to further memory elements in such a way that, from all the groups of memory elements of which a memory element is coupled to one of said read/write lines, each memory element is coupled to another of said read/write lines.

6. The semiconductor memory device as claimed in claim 2, wherein:

the memory elements of the same group are arranged in a same column; and

the groups of memory elements present in a respective column are coupled in pairs to selection transistors that are coupled to the same bit line.

7. A semiconductor memory device comprising a matrix-like arrangement of memory elements in rows and columns, the semiconductor memory device comprising:

a plurality of selection transistors, each selection transistor having two source/drain regions and an intervening channel controlled by a gate electrode, the selection transistors being arranged in rows and columns, said rows parallel to word lines and said columns parallel to bit lines;

a plurality of word lines, each word line being coupled to the gate electrodes of the selection transistors in a respective row;

a plurality of bit lines, each bit line being coupled to a respective source/drain region of a plurality of selection transistors, no two of which are arranged in the same row, wherein each selection transistor is coupled to precisely one bit line;

a plurality of memory elements formed as resistance memory elements, the memory elements being coupled row by row to read/write lines, each memory element being coupled between a respective read/write line and that source/drain region of a selection transistor that is not coupled to a bit line, wherein two successive memory elements along a read/write line are coupled to selection transistors that are coupled to different word lines;

wherein the bit lines are coupled to pairs of selection transistors that are coupled to two mutually adjacent word lines; and

wherein the selection transistors of adjacent rows along a respective word line are not coupled to mutually adjacent bit lines.

8. The semiconductor memory device as claimed in claim 7, wherein:

the bit lines run along the columns and provide addressing of each of two mutually adjacent columns of memory elements; and

the bit lines are provided with connection contacts that each make contact with a source/drain region of the selection transistors of a pair of selection transistors that are arranged in the same column and are coupled to two mutually adjacent word lines.

9. The semiconductor memory device as claimed in claim 8, wherein:

eight word lines are arranged between two connection contacts of a bit line that are present in the same column;

a plurality of word lines are arranged between two connection contacts of a bit line that are present in different columns; and

two bit lines adjacent to the relevant bit line have connection contacts that couple said bit lines to selection transistors that are not coupled to those word lines to which the selection transistors coupled to the relevant bit line are coupled.

10. The semiconductor memory device as claimed in claim 9, wherein two word lines are arranged between two connection contacts of the bit line that are present in different columns.

11. The semiconductor memory device as claimed in claim 9, wherein two word lines are arranged between four connection contacts of the bit line that are present in different columns.

12. The semiconductor memory device as claimed in claim 9, wherein two word lines are arranged between eight connection contacts of the bit line that are present in different columns.

13. The semiconductor memory device as claimed in claim 7, wherein:

the bit lines run along the columns and are provided for an addressing of four successive columns of memory elements; and

the bit lines are provided with connection contacts that make contact with a source/drain region of the selection transistors of a pair of selection transistors that are arranged in the same column and are coupled to two mutually adjacent word lines.

14. The semiconductor memory device as claimed in claim 13, wherein:

eight word lines are arranged between two connection contacts of a bit line that are present in the same column;

at least two word lines are arranged between two connection contacts of a bit line that are present in different columns; and

three columns of memory elements are present between two connection contacts arranged in the same row.

15. The semiconductor memory device as claimed in claim 14, wherein four word lines are arranged between the two connection contacts of the bit line that are present in different columns.

16. The semiconductor memory device as claimed in claim 14, wherein six word lines are arranged between the two connection contacts of the bit line that are present in different columns.

19. The semiconductor memory device as claimed in claim 8, further comprising a drive circuit integrated in the same substrate as the memory elements, the drive circuit being provided to apply electrical potentials to a selected bit line and to a selected word line for the addressing of a memory element.

20. The semiconductor memory device as claimed in claim 19, wherein the drive circuit is provided to couple a further bit line as a reference bit line with a reference resistance, the further bit line being adjacent to the selected bit line and coupled to none of the selection transistors coupled to the selected word line.