Semiconductor storage device with bit line structure disconnected in the middle of the array for reducing power consumption

• US 7,440,305 B2
• Filed: 12/21/2005
• Issued: 10/21/2008
• Est. Priority Date: 09/28/2005
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Kodama, Tsuyoshi
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US11/312,587
• Publication Number:
  US 20070070678A1
• Time in Patent Office: 1,035 Days
• Field of Search: 365/63, 365/94, 365/227
• US Class Current: 365/63
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

A semiconductor storage device comprising a plurality of memory cells disposed in an array in the row and column directions and a bit line extending in the column direction of the memory cell or a word line extending in its row direction, which is disconnected in the middle of the array.

Claims

1. A semiconductor storage device, comprising:

a plurality of memory cells disposed in an array in the row and column directions;

a bit line extending in the column direction of the memory cell or a word line extending in its row direction, which is disconnected in the middle of the array; and

a plurality of sub-word lines which is connected for every plurality of columns of the memory cell in an array and should be connected to the word line, wherein

some of the plurality of sub-word lines is not connected to the word line.

2. The semiconductor storage device according to claim 1, which is read-only memory, wherein

the disconnected bit line is connected using the same layer as used to modify data storage contents of the read-only memory.

3. The semiconductor storage device according to claim 2, wherein the same layer is a metal layer.

4. The semiconductor storage device according to claim 2, wherein the same layer is a contact layer.

5. The semiconductor storage device according to claim 1, which is read-only memory, wherein the bit line is disconnected on a boundary between a data storage area of the read-only memory and its standby data storage area.

6. The semiconductor storage device according to claim 5, wherein

the disconnected bit line is connected using the same layer as used to modify data storage contents of the read-only memory.

7. The semiconductor storage device according to claim 6, wherein the same layer is a metal layer.

8. The semiconductor storage device according to claim 6, wherein the same layer is a contact layer.

9. The semiconductor storage device according to claim 1, wherein

the bit lines are disconnected in a different position for each column of the memory cell in an array.

10. The semiconductor storage device according to claim 9, which is read-only memory, wherein

the disconnected bit line is connected using the same layer as used to modify data storage contents of the read-only memory.

11. The semiconductor storage device according to claim 10, wherein the same layer is a metal layer.

12. The semiconductor storage device according to claim 10, wherein the same layer is a contact layer.

13. The semiconductor storage device according to claim 1, wherein

the bit lines are disconnected for every plurality of rows of the memory cell in an array.

14. The semiconductor storage device according to claim 13, which is read-only memory, wherein

the disconnected bit line is connected using the same layer as used to modify data storage contents of the read-only memory.

15. The semiconductor storage device according to claim 14, wherein the same layer is a metal layer.

16. The semiconductor storage device according to claim 14, wherein the same layer is a contact layer.

17. The semiconductor storage device according to claim 1, which is read-only memory, wherein

the disconnected bit line is connected using a metal layer, and

the data storage contents of the read-only memory is modified using a contact layer.

18. The semiconductor storage device according to claim 1, wherein

the word lines are disconnected in a different position for each row of the memory cell in an array.