Semiconductor storage device with bit line structure disconnected in the middle of the array for reducing power consumption
First Claim
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1. A semiconductor storage device, comprising:
- a plurality of memory cells disposed in an array in the row and column directions;
a bit line extending in the column direction of the memory cell or a word line extending in its row direction, which is disconnected in the middle of the array; and
a plurality of sub-word lines which is connected for every plurality of columns of the memory cell in an array and should be connected to the word line, whereinsome of the plurality of sub-word lines is not connected to the word line.
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Abstract
A semiconductor storage device comprising a plurality of memory cells disposed in an array in the row and column directions and a bit line extending in the column direction of the memory cell or a word line extending in its row direction, which is disconnected in the middle of the array.
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Citations
18 Claims
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1. A semiconductor storage device, comprising:
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a plurality of memory cells disposed in an array in the row and column directions; a bit line extending in the column direction of the memory cell or a word line extending in its row direction, which is disconnected in the middle of the array; and a plurality of sub-word lines which is connected for every plurality of columns of the memory cell in an array and should be connected to the word line, wherein some of the plurality of sub-word lines is not connected to the word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification