Stacked columnar 1T-nMTj MRAM structure and its method of formation and operation

• US 7,440,339 B2
• Filed: 06/02/2005
• Issued: 10/21/2008
• Est. Priority Date: 08/08/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nejad, Hasan, Seyyedy, Mirmajid
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US11/142,448
• Publication Number:
  US 20050226038A1
• Time in Patent Office: 1,237 Days
• Field of Search: 365/189.08, 365/46, 365/63, 365/100
• US Class Current: 365/189.08
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

Claims

1. A method of reading a resistive memory device comprising a plurality of layers of resistive memory cells, each layer comprising an array of memory cells arranged in rows and columns, said method comprising:

accessing a selected memory cell by activating a row line coupled to a first side of said selected memory cell and turning on a single access transistor which couples a second side of said selected memory cell and all of the memory cells in a same column of said layer as said selected memory cell, to a sense amplifier.

2. A method as in claim 1, wherein said resistive memory cells are MRAM memory cells.

3. A method as in claim 1 further comprising sensing a resistance value of a selected memory cell with said sense amplifier.

4. A method of reading from an array of resistive memory, comprising the acts of:

selecting a desired memory cell in an X, Y, Z directional array of memory cells, memory cells arranged in Y-Z directions forming memory slices;

decoding an X direction of said desired memory cell; and

activating a single access transistor associated with said memory slice,

wherein said activated access transistor corresponds to said decoded X direction.

5. A method of reading from an array of resistive memory, comprising the acts of:

selecting a desired memory cell in an X, Y, Z directional array of memory cells, memory cells arranged in Y-Z directions forming memory slices;

decoding an Y-Z planar direction of said desired memory cell; and

selecting a read/write row line associated with said Y-Z plane; and

activating a single access transistor associated with said memory slice.

6. A method of reading from an array of resistive memory, comprising the acts of:

selecting a desired memory cell in an X, Y, Z directional array of memory cells, memory cells arranged in Y-Z directions forming memory slices;

decoding Y and Z directions of said desired memory cell; and

selecting an read/write row line associated with said Y and Z directions; and

activating a single access transistor associated with said memory slice.

7. A method of reading from an array of resistive memory, comprising the acts of:

enabling a single access transistor associated with a memory slice formed in the Y-Z direction containing a desired memory cell for reading;

coupling said memory slice to a sense amplifier; and

coupling a non selected memory slice to said sense amplifier to use as a reference.

8. The method of reading of claim 7, further comprising the act of:

coupling said desired memory cell to a sense line.

9. The method of reading of claim 7, wherein said decoding further comprises:

determining a row, column and memory slice associated with said desired memory cell.