Queue management of a global link control byte in an input/output subsystem

• US 7,440,468 B2
• Filed: 12/11/2003
• Issued: 10/21/2008
• Est. Priority Date: 12/11/2003
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jestes, Roger C. Jr.
• Primary Examiner(s): Kang; Suk Jin
• Application Number:
  US10/734,033
• Publication Number:
  US 20050129041A1
• Time in Patent Office: 1,776 Days
• Field of Search: 370/412
• US Class Current: 370/412
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9021 Plurality of buffers per packet

Abstract

Method and apparatus for communicating global link control words (LCW) between chips. A queue stores LCWs and has in input for receiving an LCW from a previous chip, and an output for outputting a stored LCW to a subsequent chip. A management circuit compares an incoming LCW with a previously stored LCW, and a combiner circuit combines the incoming LCW with a previously stored LCW and stores the combined LCW in the queue when the management circuit determines that the incoming LCW can be combined with the previously stored LCW.

Claims

1. A method for communicating global link control words (LCW) between chips, said method comprising:

storing an LCW in a queue, said queue having an input for receiving an LCW from a previous chip, and an output for outputting a stored LCW to a subsequent chip;

comparing with a management circuit, an incoming LCW with a previously stored LCW; and

combining the incoming LCW with a previously stored LCW and storing the combined LCW in said queue when said management circuit determines that the incoming LCW can be combined with the previously stored LCW such that more than one LCW are combined into a combined LCE; and

storing the combined LCWs in an element of said queue.

2. The method according to claim 1 further comprising storing in a separate element of said queue, said incoming LCW when it is determined in said determining step that the incoming LCW cannot be combined with the previously stored LCW.

3. The method according to claim 1 wherein each LCW comprises bits and said combining step comprises combining the bits of said incoming LCW with the bits of said previously stored LCW with an OR circuit.

4. The method according to claim 3 further comprising placing a control bit in a first state by said management circuit indicating that the incoming LCW cannot be combined with another LCW previously stored in said queue for controlling storing said incoming LCW in a separate element in said queue, and placing said control bit in a second state by said management circuit indicating said incoming LCW can be combined with another LCW previously stored in said queue.

5. The method according to claim 3 wherein at least two selected bits of said LCWs have an Exclusive OR relationship wherein either of the bits may be on, but not both, and said combining step comprises preventing the combining of two LCWs if the Exclusive OR relationship is violated.