Method and apparatus for a two-wire serial command bus interface

• US 7,441,065 B2
• Filed: 03/01/2007
• Issued: 10/21/2008
• Est. Priority Date: 06/13/2002
• Status: Expired due to Term

• Current Assignee: Koninklijke Philips N.V.
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Lyle, Jim
• Primary Examiner(s): Knoll; Clifford H
• Application Number:
  US11/713,241
• Publication Number:
  US 20070150629A1
• Time in Patent Office: 600 Days
• Field of Search: 710/310, 710/52
• US Class Current: 710/310
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: H04L 63/02 for separating internal from external traffic, e.g. firewalls
• CPC Class Codes: H04L 69/08 Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/24 Negotiation of communication capabilities

Abstract

A method for bi-directional transmission of data between a source and a sink over a two-wire interface includes re-mapping a data signal and a clock signal from a first local bus on the source into a different protocol signal. Transmitting the different protocol signal from the source to the sink over the two-wire interface. Re-mapping the different protocol signal back into the data signal and the clock signal for use on a second local bus on the sink. Re-mapping the data signal and the clock signal from the second local bus into the different protocol signal; and transmitting the different protocol signal from the sink to the source over the two-wire interface.

Claims

1. A system for bi-directional transmission of data between a source and sink over a Display Data Channel (DDC) compatible two-wire interface, the system comprising:

a first translator responsive to and operative to develop a first local I²C bus signal for signal current flow in a first direction and responsive to and operative to develop a different protocol signal over the DDC-compatible two-wire interface for signal current flow in a second direction;

the first translator including an I²C port for converting serial data signal and serial clock signal into internal signal blocks, a translation logic for translating the internal signal blocks to the different protocol signal, and a physical interface for interfacing the translated different protocol signal onto the DDC-compatible two-wire interface;

a first buffer responsive to and operative to develop the first local I²C bus signal for signal current flow in the first direction and responsive to and operative to develop a buffered signal including a buffered data signal and a buffered clock signal for signal current flow in the second direction;

the first buffer including a first data buffer circuit for assisting the current flow of the serial data signal to extend the distance over which the serial data signal may be communicated, and a first clock buffer circuit for assisting the current flow of the serial clock signal to extend the distance over which the serial clock signal may be communicated;

the buffered data signal being communicated over a first wire of the DDC-compatible two-wire interface and the buffered clock signal being communicated over a second wire of the DDC-compatible two-wire interface;

a logic responsive to the first local I²C bus signal and operative to control a first switch coupled to the DDC-compatible two-wire interface wherein the first switch connects the DDC-compatible two-wire interface to one of the first translator, the first buffer, and an isolation firewall in which electrical access to the source via the DDC two-wire interface is cut off;

a second translator responsive to and operative to develop the different protocol signal for signal current flow in the first direction and responsive to and operative to develop a second local I²C bus signal for signal current flow in the second direction when the first switch is connected to the first translator and a second switch coupled to the DDC-compatible two-wire interface is connected to the second translator; and

a second buffer responsive to and operative to develop the buffered signal including the buffered data signal and the buffered clock signal for signal current flow in the second direction; and

responsive to and operative to develop the second local I²C bus signal for signal current flow in the first direction when the first switch is connected to the first buffer and the second switch coupled to the DDC-compatible two-wire interface is connected to the second buffer.

2. The system as recited in claim 1 wherein the different protocol signal is defined in an ethernet protocol.

3. The system as recited in claim 1 wherein different protocol signal is defined in a TCP/IP protocol.

4. The system as recited in claim 1 wherein the different protocol signal is defined in an RS-232 protocol.

5. The system as recited in claim 1 wherein the different protocol signal is defined in a current loop protocol.

6. A method for buffering signals between a source and a sink over a Display Data Channel (DDC) compatible two-wire interface comprising:

buffering on the source a serial data signal and a serial clock signal received from a local I²C bus on the source;

transmitting from the source to the sink the serial data signal and the serial clock signal over the DDC-compatible two-wire interface;

buffering at the sink the data and clock signals, the buffering including buffering the data signal to assist the current flow of the serial data signal to extend the distance over which the serial data signal may be communicated, and buffering the clock signal to assist the current flow of the serial clock signal to extend the distance over which the serial clock signal may be communicated;

communicating the buffered data signal over a first wire of the DDC-compatible two-wire interface and the buffered clock signal being communicated over a second wire of the DDC-compatible two-wire interface, the buffing further including sensing a direction of current flow and assisting the current flow in the sensed direction to extend the distance over which the clock signal and the data signal may be communicated;

re-transmitting from the sink the data and clock signals over the DDC-compatible two-wire interface to the source as needed; and

performing an isolation firewall function by selectively switching to an isolation firewall setting to close access from the source to the DDC-compatible two-wire interface.

7. A system for buffering signals between a source and a sink over a Display Data Channel (DDC) compatible two-wire interface comprising:

a first buffer responsive to a first I²C local bus signal and responsive to and operative to develop a buffered serial data signal and a buffered serial clock signal;

the first buffer including a first data buffer circuit for assisting the current flow of the serial data signal to extend the distance over which the serial data signal may be communicated, and a first clock buffer circuit for assisting the current flow of the serial clock signal to extend the distance over which the serial clock signal may be communicated;

the buffered data signal being communicated over a first wire of the DDC compatible two-wire interface and the buffered clock signal being communicated over a second wire of the DDC compatible two-wire interface;

a logic responsive to the first local bus signal and operative to controlling a first switch coupled to the DDC-compatible two-wire interface wherein the switch connects to the first buffer or an isolation firewall setting in which electrical access to the source via the DDC two-wire interface is cut off; and

a second buffer responsive to and operative to develop the buffered data signal and the buffered clock signal and responsive to and operative to develop a second I²C local bus signal when the first switch is connected to the first buffer and a second switch coupled to the DDC-compatible two-wire interface is connected to the second buffer.

8. A system for buffering signals between a source and a sink over a two-wire interface comprising:

a first buffer responsive to a first local bus signal and operative to develop a buffered serial data signal and a buffered serial clock signal from the first local bus signal, the first buffer including a first data buffer circuit for assisting the current flow of the serial data signal to extend the distance over which the serial data signal may be communicated, and a first clock buffer circuit for assisting the current flow of the serial clock signal to extend the distance over which the serial clock signal may be communicated;

the buffered serial data signal being communicated over a first wire of the DDC-compatible two-wire interface and the buffered serial clock signal being communicated over a second wire of the DDC-compatible two-wire interface;

a logic responsive to the first local bus and operative to controlling a first switch coupled to the two-wire interface wherein the switch connects to one of the first buffer and an isolation firewall setting; and

the sink coupled to the two-wire interface and responsive to the buffered data signal and the buffered clock signal when the switch is connected to the first buffer.

9. A system for bi-directional transmission of data between a source and sink over a Display Data Channel (DDC) compatible two-wire interface, the system comprising:

a first translator responsive to and operative to develop a first local bus signal and responsive to and operative to develop a different protocol signal over the DDC-compatible two-wire interface;

a first buffer responsive to and operative to develop the first local bus signal and responsive to and operative to develop a buffered signal including a buffered data signal and a buffered clock signal;

a logic responsive to the first local bus signal and operative to control a first switch coupled to the DDC-compatible two-wire interface wherein the first switch connects the DDC-compatible two-wire interface to one of the first translator and the first buffer;

a second translator responsive to and operative to develop the different protocol signal and responsive to and operative to develop a second local bus signal when the first switch is connected to the first translator and a second switch coupled to the DDC-compatible two-wire interface is connected to the second translator; and

a second buffer responsive to and operative to develop the buffered signal including the buffered data signal and the buffered clock signal; and

responsive to and operative to develop the second local bus signal when the first switch is connected to the first buffer and the second switch coupled to the DDC-compatible two-wire interface is connected to the second buffer.

10. The system as recited in claim 9, wherein:

the first buffer including a first data buffer circuit for assisting the current flow of the serial data signal to extend the distance over which the serial data signal may be communicated, and a first clock buffer circuit for assisting the current flow of the serial clock signal to extend the distance over which the serial clock signal may be communicated; and

the buffered data signal being communicated over a first wire of the DDC-compatible two-wire interface and the buffered clock signal being communicated over a second wire of the DDC-compatible two-wire interface.

11. The system as recited in claim 9, wherein:

the first translator for converting serial data signals and serial clock signals into internal signal blocks, a translation logic for translating the internal signal blocks to the different protocol signal, and a physical interface for interfacing the translated different protocol signal onto the DDC-compatible two-wire interface.

12. The system as recited in claim 9, wherein:

the first switch connects the DDC-compatible two-wire interface to one of the first translator, the first buffer, and an isolation firewall in which electrical access to the source via the DDC two-wire interface is cut off.

13. The system as recited in claim 9, wherein the different protocol signal is a protocol selected from the set consisting of an Ethernet protocol, a TCP/IP protocol, an RS-232 protocol, and a current loop protocol.

14. A method for buffering signals between a source and a sink over a two-wire interface comprising:

buffering on the source a serial data signal and a serial clock signal received from a local bus on the source;

transmitting from the source to the sink the serial data signal and the serial clock signal over the two-wire interface;

buffering at the sink the data and clock signals, the buffering including buffering the data signal to assist the current flow of the serial data signal to extend the distance over which the serial data signal may be communicated, and buffering the clock signal to assist the current flow of the serial clock signal to extend the distance over which the serial clock signal may be communicated;

communicating the buffered data signal over a first wire of the two-wire interface and the buffered clock signal being communicated over a second wire of the two-wire interface, the buffing further including sensing a direction of current flow and assisting the current flow in the sensed direction to extend the distance over which the clock signal and the data signal may be communicated; and

re-transmitting from the sink the data and clock signals over the two-wire interface to the source as needed.

15. The method as recited in claim 14, wherein:

the two-wire interface comprises a Display Data Channel (DDC) compatible two-wire interface and the local bus comprises a local I²C bus.

16. The method as recited in claim 14, further comprising:

performing an isolation firewall function by selectively switching to an isolation firewall setting to close access from the source to the two-wire interface.