Testing apparatus and testing method

• US 7,441,166 B2
• Filed: 09/01/2006
• Issued: 10/21/2008
• Est. Priority Date: 03/24/2004
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Sato, Kazuhiko, Yamada, Masuhiro, Ohsawa, Toshimi
• Primary Examiner(s): Chung; Phung M
• Application Number:
  US11/515,350
• Publication Number:
  US 20070067685A1
• Time in Patent Office: 781 Days
• Field of Search: 714/718, 714/719, 714/724, 714/736, 714/738, 714/819, 365/200, 365/201
• US Class Current: 714/718
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56004 Pattern generation

Abstract

There is provided a testing apparatus including: a pattern generator that generates an address signal and a data signal to be supplied to a plurality of memories under test and an expectation signal; a plurality of logic comparators that generate fail data when an output signal output from the plurality of memories under test and the expectation signal are not identical with each other; a plurality of fail memories that store the fail data generated from the plurality of logic comparators; a plurality of memory controllers that generate bad address information showing a bad address in the memory under test based on the fail data stored on the plurality of fail memories; a plurality of universal buffer memories that store the bad address information generated from the plurality of memory controllers; and a plurality of bad information writing sections that concurrently write bad information into the bad address in the plurality of memories under test, which is shown by the bad address information stored on the plurality of universal buffer memories.

Claims

1. A testing apparatus that concurrently tests a plurality of memories under test, comprising:

a pattern generator that generates an address signal and a data signal to be supplied to each of the plurality of memories under test and an expectation signal to be output from each memory under test according to the address signal and the data signal;

a plurality of logic comparators, each of which being provided corresponding to one of the memories under test and comparing an output signal output from the corresponding memory under test according to the address signal and the data signal with the expectation signal to generate fail data when the output signal is not identical with the expectation signal;

a plurality of fail memories, each of which being provided corresponding to one of the memories under test and storing the fail data generated by the corresponding logic comparator in association with an address shown by the address signal;

a plurality of memory controllers, each of which being provided corresponding to one of the memories under test and generating bad address information showing a bad address in the corresponding memory under test based on the fail data stored on the corresponding fail memory;

a plurality of universal buffer memories, each of which being provided corresponding to one of the memories under test and storing the bad address information generated from the corresponding memory controller; and

a plurality of bad information writing sections, each of which being provided corresponding to one of the memories under test and writing first bad information into the bad address in the corresponding memory under test, the bad address being shown by the bad address information stored on the corresponding universal buffer memory, the writing first bad information being performed concurrently for the plurality of memories under test.

2. The testing apparatus as claimed in claim 1, further comprising:

a plurality of first buses that respectively connect the plurality of fail memories to the plurality of memory controllers; and

a plurality of second buses that respectively connect the plurality of memory controllers to the plurality of universal buffer memories.

3. The testing apparatus as claimed in claim 1, wherein each of the memory controllers generates the bad address information with a format peculiar to the corresponding memory under test and supplies the generated information to the corresponding universal buffer memory.

4. The testing apparatus as claimed in claim 3, wherein each of the memory controllers operates based on a program loaded according to a type of the corresponding memory under test in order to generate the bad address information with the format peculiar to the corresponding memory under test.

5. The testing apparatus as claimed in claim 1, wherein each memory under test comprises a plurality of block areas each having a plurality of page areas, each page area including a main area storing data and an extended area storing the first bad information,

each fail memory stores the fail data on each of the block areas in the corresponding memory under test,

each memory controller generates the bad address information showing a block address of a defective of the block areas in the corresponding memory under test with reference to the corresponding fail memory,

each universal buffer memory stores the bad address information generated from the corresponding memory controller, and

each bad information writing section writes first bad information into the extended area in the block area shown by the bad address information stored on the corresponding universal buffer memory.

6. The testing apparatus as claimed in claim 5, wherein the pattern generator generates a page address signal showing the page area to supply the generated signal to the plurality of bad information writing sections, and the plurality of bad information writing sections write the first bad information into the extended area in the page area shown by the page address signal generated from the pattern generator.

7. The testing apparatus as claimed in claim 1, wherein each memory controller comprises:

a data reading section that reads data stored on a predetermined address of the corresponding fail memory;

a fail judging section that judges whether or not the fail data are included in the data read by the data reading section; and

a bad address information generating section that generates the bad address information when the fail judging section judges that the fail data are included in the data read by the data reading section.

8. The testing apparatus as claimed in claim 1, wherein

each memory controller generates second bad information with a format peculiar to the corresponding memory under test based on the fail data stored on the corresponding fail memory,

each universal buffer memory stores the second bad information generated by the corresponding memory controller, and

each bad information writing section writes the second bad information stored on the corresponding universal buffer memory into the plurality of memories under test into the corresponding memory under test.

9. The testing apparatus as claimed in claim 8, wherein each memory controller operates based on a program loaded according to a type of the corresponding memory under test in order to generate the second bad information with the format peculiar to the corresponding memory under test.

10. The testing apparatus as claimed in claim 8, further comprising:

a plurality of first fail information memories, each of which being provided corresponding to one of the memories under test and storing the second bad information generated by the corresponding memory controller;

a plurality of second fail information memories, each of which being provided corresponding to one of the memories under test and storing the second bad information read from the corresponding memory under test; and

a quality deciding section that compares each second bad information stored on each first fail information memory with each second bad information stored on the corresponding second fail information memory to decide whether each memory under test is defective.

11. The testing apparatus as claimed in claim 10, further comprising:

a plurality of first buses that respectively connect the plurality of fail memories and the plurality of first fail information memories to the plurality of memory controllers; and

a plurality of second buses that respectively connect the plurality of memory controllers to the plurality of universal buffer memories.

12. The testing apparatus as claimed in claim 11, wherein each memory under test comprises a plurality of main areas storing data and a special area storing the second bad information, and

each bad information writing section writes the second bad information into the special area included in the corresponding memory under test.

13. A testing apparatus that concurrently tests a plurality of memories under test, comprising:

a pattern generator that generates an address signal and a data signal to be supplied to each of the plurality of memories under test and an expectation signal to be output from each memory under test according to the address signal and the data signal;

a plurality of logic comparators, each of which being provided corresponding to one of the memories under test and comparing an output signal output from the corresponding memory under test according to the address signal and the data signal and the expectation signal to generate fail data when the output signal is not identical with the expectation signal;

a plurality of fail memories, each of which being provided corresponding to one of the memories under test and storing the fail data generated by the corresponding logical comparator in association with an address shown by the address signal;

a plurality of memory controllers, each of which being provided corresponding to one of the memories under test and generating bad information with a format peculiar to each memory under test based on the fail data stored on the corresponding fail memory;

a plurality of universal buffer memories, each of which being provided corresponding to one of the memories under test and storing the bad information generated from the corresponding memory controller; and

a plurality of bad information writing sections, each of which being provided corresponding to one of the memories under test and writing the bad information stored on the corresponding universal buffer memory, the writing the bad information being performed concurrently for the plurality of memories under test.

14. A testing method for concurrently testing a plurality of memories under test, comprising:

generating an address signal and a data signal to be supplied to each of the plurality of memories under test and an expectation signal to be output from each memory under test according to the address signal and the data signal;

comparing an output signal output from each memory under test according to the address signal and the data signal with the expectation signal to generate fail data when the output signal is not identical with the expectation signal by means of a plurality of logic comparators, each of which is provided corresponding to one of the memories under test;

storing the fail data in association with an address shown by the address signal on a plurality of fail memories, each of which is provided corresponding to one of the memories under test;

generating bad address information showing a bad address in each memory under test based on the fail data stored on the corresponding fail memory by means of a plurality of memory controllers, each of which is provided corresponding to one of the memories under test;

storing the bad address information generated by each memory controller on a plurality of universal buffer memories, each of which is provided corresponding to one of the memories under test; and

writing a first bad information into the bad address in each memory under test, the bad address being shown by the bad address information stored on the corresponding universal buffer memory by means of a plurality of bad information writing sections, each of which is provided corresponding to one of the memories under test, the writing the first bad information being performed concurrently for the plurality of memories under test.

15. A testing method for concurrently testing a plurality of memories under test, comprising:

generating an address signal and a data signal to be supplied to each of the plurality of memories under test and an expectation signal to be output from each memory under test according to the address signal and the data signal;

comparing an output signal output from each memory under test according to the address signal and the data signal with the expectation signal to generate fail data when the output signal is not identical with the expectation signal by means of a plurality of logic comparators, each of which is provided corresponding to one of the memories under test;

storing the fail data generated by each logic comparator in association with an address shown by the address signal by means of a plurality of fail memories, each of which is provided corresponding to one of the memories under test;

generating bad information with a format peculiar to each memory under test based on the fail data stored on the corresponding fail memory by means of a plurality of memory controllers, each of which is provided corresponding to one of the memories under test;

storing the bad information generated by each memory controller by means of a plurality of universal buffer memories, each of which is provided corresponding to one of the memories under test; and

writing the bad information stored on each universal buffer memory into the corresponding memory under test by means of a plurality of bad information writing sections, each of which is provided corresponding to one of the memories under test, the writing the bad information being performed concurrently for the plurality of memories under test.