Systems, devices, and methods for arc fault detection

• US 7,441,173 B2
• Filed: 02/16/2006
• Issued: 10/21/2008
• Est. Priority Date: 02/16/2006
• Status: Active Grant

• Current Assignee: Siemens Industry Incorporated (Siemens AG)
• Original Assignee: Siemens Energy & Automation Incorporated (Siemens AG)
• Inventors: Zhang, Bin, Restrepo, Carlos
• Primary Examiner(s): Ton; David
• Application Number:
  US11/355,676
• Publication Number:
  US 20070208981A1
• Time in Patent Office: 978 Days
• Field of Search: 361/96, 361/45, 361/54, 361/42, 361/2, 361/103, 700/293, 324/521, 714/745, 714/47
• US Class Current: 714/745
• CPC Class Codes: H02H 1/0015 Using arc detectors
• CPC Class Codes: H02H 3/334 with means to produce an artificial unbalance for other protection or monitoring reasons or remote control H02H3/338 takes precedence

Abstract

Certain exemplary embodiments comprise a system that comprises an application specific integrated circuit configured to provide an output signal. The output signal can be configured to trip a device in an electrical circuit responsive to a detected fault. The application specific integrated circuit can comprise a temperature sensor. The application specific integrated circuit can be configured to correct at least one measured electrical value responsive to a temperature measured by the temperature sensor.

Claims

1. A system comprising:

an application specific integrated circuit configured to provide an output signal, said output signal configured to trip a device in an electrical circuit responsive to a detected fault, said application specific integrated circuit comprising;

an on-chip linear temperature sensor, said application specific integrated circuit configured to correct at least one measured electrical value responsive to a temperature measured by said on-chip linear temperature sensor; and

a level and timing control circuit configured to avoid nuisance trips caused by noise in a received signal from said electrical circuit, said level and timing control circuit configured to compare an amplitude of said received signal to a first predetermined threshold, said level and timing control circuit configured to compare a duration of said received signal to a second predetermined threshold.

2. The system of claim 1, said application specific integrated circuit further comprising:

a power up reset circuit configured to avoid nuisance trips during a system power up.

3. The system of claim 1, said application specific integrated circuit further comprising:

a simulation circuit configured to simulate a signal indicative of an arc fault to an input of said application specific integrated circuit, said input generated responsive to an action of a user.

4. The system of claim 1, said application specific integrated circuit further comprising:

an oscillator circuit configured to control a simulated waveform frequency of a simulation circuit.

5. The system of claim 1, said application specific integrated circuit further comprising:

a circuit configured to receive an input for a ground fault.

6. The system of claim 1, said application specific integrated circuit further comprising:

a circuit configured to control a gain of a circuit configured to receive a ground fault input signal.

7. The system of claim 1, said application specific integrated circuit further comprising:

a circuit configured to control a time delay associated with a ground fault input signal.

8. The system of claim 1, said application specific integrated circuit further comprising:

a circuit configured to control a status of a silicon-controlled rectifier.

9. The system of claim 1, said application specific integrated circuit further comprising:

a circuit configured to control an arc fault integration.

10. The system of claim 1, said application specific integrated circuit further comprising:

a circuit configured to phase-shift an arc fault signal.

11. The system of claim 1, said application specific integrated circuit further comprising:

a circuit configured to control a gain of a circuit configured to receive an input for an arc fault.

12. The system of claim 1, said application specific integrated circuit further comprising:

a circuit configured to control an arc fault signal amplitude.

13. The system of claim 1, said application specific integrated circuit further comprising:

a circuit configured to receive an input from a neutral line current sensor.

14. The system of claim 1, said application specific integrated circuit further comprising:

a circuit configured to receive an arc fault input signal.

15. The system of claim 1, said application specific integrated circuit further comprising:

a control circuit configured to react rapidly to a strong arc fault.

16. The system of claim 1, said application specific integrated circuit further comprising:

a control circuit configured to react rapidly to a ground fault.

17. The system of claim 1, said application specific integrated circuit further comprising:

a voltage regulator configured to provide a voltage output from said application specific integrated circuit.

18. The system of claim 1, further comprising:

a power supply.

19. The system of claim 1, further comprising:

a mechanism configured to trip said device in said electrical circuit.

20. The system of claim 1, further comprising:

a sensor configured to measure a neutral current in said electrical circuit.

21. The system of claim 1, further comprising:

a sensor configured to measure a differential current in said electrical circuit.

22. A method comprising:

producing an application specific integrated circuit configured to provide an output signal, said output signal configured to trip a device in an electrical circuit responsive to a detected fault, said application specific integrated circuit comprising;

an on-chip linear temperature sensor, said application specific integrated circuit configured to correct at least one measured electrical value responsive to a temperature measured by said on-chip linear temperature sensor; and

a level and timing control circuit configured to avoid nuisance trips due to noise in a received signal from said electrical circuit, said level and timing control circuit configured to compare an amplitude of said received signal to a first predetermined threshold, said level and timing control circuit configured to compare a duration of said received signal to a second predetermined threshold.

23. An application specific integrated circuit comprising:

an output circuit configured to provide an output signal, said output signal configured to trip a device in an electrical circuit responsive to a detected fault;

an on-chip linear temperature sensor, said application specific integrated circuit configured to correct at least one measured electrical value responsive to a temperature measured by said on-chip linear temperature sensor; and

a level and timing control circuit configured to avoid nuisance trips caused by noise in a received signal from said electrical circuit, said level and timing control circuit configured to compare an amplitude of said received signal to a first predetermined threshold, said level and timing control circuit configured to compare a duration of said received signal to a second predetermined threshold.