Local preferred direction architecture, tools, and apparatus

• US 7,441,220 B2
• Filed: 12/06/2004
• Issued: 10/21/2008
• Est. Priority Date: 12/07/2000
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Fujimura, Akira, King, Roger, Hetzel, Asmus, Jacques, Etienne, Malhotra, Anish, Frankle, Jon, Harrison, David S., Feather, Heath, Matveev, Alexandre
• Primary Examiner(s): Siek; Vuthe
• Application Number:
  US11/005,316
• Publication Number:
  US 20050229134A1
• Time in Patent Office: 1,415 Days
• Field of Search: 716 12- 15
• US Class Current: 716/135
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring model allows at least one wiring layer to have a set of regions that each have a different preferred direction than the particular wiring layer. In addition, each region has a local preferred direction that differs from the local preferred direction of at least one other region in the set. Furthermore, at least two regions have two different polygonal shapes and no region in the set encompasses another region in the set. Some embodiments also provide a Graphical User Interface (GUI) that facilitates a visual presentation of an LPD design layout and provides tools to create and manipulate LPD regions in a design layout.

Claims

1. A design layout comprising:

a plurality of routing layers; and

a first polygonally shaped region and a second polygonally shaped region on one of the layers, the first region having a first local preferred routing direction and the second region having a second local preferred routing direction that is different than the first local preferred routing direction, wherein a local preferred routing direction of a region defines a preferred direction for defining routes in the region, wherein the first region has a different shape than the second region, wherein the first region is in the shape of a non-quadrilateral polygon,

wherein the first region does not encompass the second region and the second region does not encompass the first region.

2. The layout of claim 1, wherein the second region is in the shape of a quadrilateral polygon.

3. The layout of claim 1, wherein the second region is in the shape of a non-quadrilateral polygon.

4. The layout of claim 1, wherein the first region has more than four sides.

5. The layout of claim 1, wherein the first region is in the shape of an octagon.

6. The layout of claim 1, wherein the first region is in the shape of a hexagon.

7. The layout of claim 1, wherein the first and second regions have a Manhattan local preferred wiring direction.

8. The layout of claim 1, wherein the first and second regions have a diagonal local preferred wiring direction.

9. The layout of claim 8, wherein the diagonal local preferred wiring directions are orthogonal to each other.

10. The layout of claim 8, wherein the diagonal local preferred wiring directions are neither parallel nor orthogonal to each other.

11. The layout of claim 1, wherein the second region has a Manhattan local preferred wiring direction and the first region has a diagonal local preferred wiring direction.

12. The layout of claim 1, wherein the design layout is an integrated circuit layout.

13. A design layout comprising:

a plurality of routing layers; and

a first local preferred direction (“

LPD”

) region and a second LPD region on one of the layers, the first LPD region having a first polygonal shape and a first local preferred routing direction, the second LPD region having a second polygonal shape and a second local preferred routing direction that is different than the first local preferred routing direction, wherein routes that traverse in a non-preferred direction are penalized while routes that traverse in a preferred direction are not, wherein the first and second LPD regions have two different polygonal shapes, wherein each polygonal shape is a convex polygon.

14. The design layout of claim 13, wherein the design layout is for an integrated circuit.

15. A multi-layer design layout comprising:

a first wiring layer having at least one pre-designed circuit block having a preferred wiring direction; and

a second wiring layer positioned directly adjacent to said first wiring layer, wherein said second wiring layer has at least one region adjacent to said pre-designed circuit block, said region having a local preferred wiring direction parallel or orthogonal to the preferred wiring direction of said at least one pre-designed circuit block,

wherein the local preferred wiring direction of the region defines a preferred direction for defining wires in the region,

wherein the local preferred wiring direction of the region is different than a preferred wiring direction of at least one other region on the second wiring layer.

16. The multi-layer design layout of claim 15, wherein said second wiring layer has a diagonal preferred wiring direction.

17. The multi-layer design layout of claim 16, wherein said at least one region has a Manhattan local preferred wiring direction.

18. The multi-layer design layout of claim 15, wherein a pre-designed circuit block is an IP block.

19. The multi-layer design layout of claim 15, wherein one wiring layer is above another wiring layer.

20. The multi-layer design layout of claim 15, wherein a first region is above the pre-designed circuit block, wherein the first region has the shape of a non-quadrilateral.

21. The multi-layer design layout of claim 15, wherein the multi-layer design layout is for a multi-layer integrated circuit design layout.

22. An integrated circuit (“

IC”

) comprising;

a plurality of wiring layers; and

a first polygonally shaped region and a second polygonally shaped region on one of the layers, the first region having a first local preferred wiring direction, the second region having a second local preferred wiring direction that is different than the first local preferred wiring direction, wherein a preferred wiring direction of a region is a direction in which a majority of the wires in the region have to traverse, wherein the first region has a different shape than the second region, wherein the first region is in the shape of a non-quadrilateral polygon,

wherein the first region does not encompass the second region and the second region does not encompass the first region.

23. The IC of claim 22, wherein the second region is in the shape of a quadrilateral.

24. The IC of claim 22, wherein the second region is in the shape of a non-quadrilateral.

25. The IC of claim 22, wherein the first region has more than four sides.

26. The IC of claim 22, wherein the first and second regions have a Manhattan local preferred wiring direction.

27. The IC of claim 22, wherein the first and second regions have a diagonal local preferred wiring direction.

28. The IC of claim 27, wherein the diagonal local preferred wiring directions are orthogonal to each other.

29. The IC of claim 27, wherein the diagonal local preferred wiring directions are neither parallel nor orthogonal to each other.

30. The IC of claim 22, wherein the second region has a Manhattan local preferred wiring direction and the first region has a diagonal local preferred wiring direction.

31. The IC of claim 22, wherein the first region has a Manhattan local preferred wiring direction and the second region has a diagonal local preferred wiring direction.

32. The IC of claim 22, wherein the majority of routes in the region is defined as at least 50% of the wires in the region.

33. The IC of claim 22, wherein the majority of routes in the region is defined as at least 1000 wires in the region.

34. A multi-layer integrated circuit comprising:

a first wiring layer having at least one pre-designed circuit block having a preferred wiring direction; and

a second wiring layer positioned directly adjacent to said first wiring layer, wherein said second wiring layer has at least one region adjacent to said pre-designed circuit block, said region having a local preferred wiring direction parallel or orthogonal to the preferred wiring direction of said at least one pre-designed circuit block,

wherein the local preferred wiring direction of the region defines a preferred direction of wires in the region,

wherein the local preferred wiring direction of the region is different than a preferred wiring direction of at least one other region on the second wiring layer.

35. The multi-layer IC of claim 34, wherein said second wiring layer has a diagonal preferred wiring direction.

36. The multi-layer IC of claim 35, wherein said at least one region has a Manhattan local preferred wiring direction.

37. The multi-layer IC of claim 34, wherein a pre-designed circuit block is an IP block.

38. The multi-layer IC of claim 34, wherein one wiring layer is above another wiring layer.

39. The multi-layer IC of claim 34, wherein a first region is above the pre-designed circuit block, wherein the first region has the shape of a non-quadrilateral.