High dynamic range cascaded integration pixel cell

• US 7,442,910 B2
• Filed: 03/24/2005
• Issued: 10/28/2008
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Fossum, Eric R.
• Primary Examiner(s): Epps; Georgia Y.
• Assistant Examiner(s): Legasse, Jr.; Francis M
• Application Number:
  US11/088,978
• Publication Number:
  US 20050168608A1
• Time in Patent Office: 1,314 Days
• Field of Search: 250/208.1, 250/214.R, 250/214.1, 348/254, 348/295, 348/302, 257/222, 257/223, 257/225, 257/292
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A cascaded imaging storage system for a pixel is disclosed for improving intrascene dynamic range. Charges accumulated in a first capacitor spill over into a second capacitor when a charge storage capacity of the first capacitor is exceeded. A third capacitor may also be provided such that charges accumulated by said second capacitor spill over into the third capacitor when the charge storage capacity of the second capacitor is exceeded.

Claims

1. An imager pixel cell comprising:

a photo-conversion device for generating electrical charges in response to photon energy impinging thereon;

a first capacitor associated with the photo-conversion device;

a first transistor electrically coupled to the photo-conversion device for resetting the device to a particular voltage;

a second transistor coupled to the photo-conversion device for coupling a second capacitor for accumulating charge converted by the photo-conversion device when the converted charge exceeds a first threshold value during the integration period;

a source follower transistor having a gate for receiving the electrical charges; and

a row select transistor for coupling the output of the source follower transistor to an output line.

2. The imager pixel cell of claim 1, further comprising a second transistor coupled to the photo-conversion device for coupling a third capacitor for accumulating charge when the converted charge exceeds a second threshold.

3. The imager pixel cell of claim 1, wherein the first capacitor is a parasitic capacitance associated with the photo-conversion device.

4. The pixel cell of claim 3, wherein the photo-conversion device is a photodiode.

5. The imager pixel cell of claim 1, wherein the first capacitor is a discrete capacitor connected to the photo-conversion device.

6. The imager pixel cell of claim 1, wherein the second capacitor has a capacitance value greater that the first capacitor.

7. The imager pixel cell of claim 2, wherein the second capacitor has a capacitance value greater than the first capacitor and the third capacitor has a capacitance value greater than the second capacitor.

8. An imager pixel cell comprising:

a photo-conversion device for generating electrical charges in response to photon energy impinging thereon;

a first reset transistor for resetting the photo-conversion device to a predetermined voltage during a reset period;

a storage system for storing the electrical charges, the storage system comprising a sequence of capacitors arranged such that a later capacitor in a sequence stores charge which overflows from an earlier capacitor in the sequence during an integration period;

a source follower transistor having a gate for receiving the electrical charges; and

a row select transistor for coupling the output of the source follower transistor to an output line.

9. The imager pixel cell of claim 8, wherein the sequence of capacitors comprises a first and second capacitor.

10. The imager pixel cell of claim 8, wherein the sequence of capacitors comprises a first, second and third capacitor.

11. The imager pixel cell of claim 8, wherein the sequence of capacitors stores charge in a sequential fashion.

12. The imager pixel cell of claim 8, wherein the storage system further comprises a transfer transistor for controlling charge transfer from an earlier capacitor to a later capacitor in the sequence and wherein the flow of charge from a the earlier capacitor to the later capacitor is determined by a barrier potential set by the transfer transistor.

13. The imager pixel cell of claim 12, wherein the barrier potential is variable in accordance with a gate voltage applied to the transfer transistor.

14. The imager pixel cell of claim 12, wherein a first of the capacitors in the sequence receives and stores charges directly from the conversion device, while a later capacitor in the sequence receives charges from the photo-conversion device through the transfer transistor.

15. The imager pixel cell of claim 10, wherein the second capacitor is connected to the photo-conversion device through a second transfer transistor and the third capacitor is connected to the photo-conversion device through a third transfer transistor.

16. The imager pixel cell of claim 15, wherein the second transistor directly couples the second capacitor to the photo-conversion device.

17. The imager pixel cell of claim 15, wherein the third transistor directly couples the third capacitor to the photo-conversion device.

18. The imager pixel cell of claim 15, wherein the third transistor couples the third capacitor to the photo-conversion device through the second transistor.

19. The imager pixel cell of claim 15, wherein the second and third transistors respectively set barrier potentials which must be exceeded before the second and third capacitors respectively begin to storage charges.

20. The imager pixel cell of claim 19, wherein the barrier potentials are adjustable by gate voltages applied to the second and third transistors.

21. The imager pixel cell of claim 8, wherein the first reset transistor is arranged to apply a reset voltage directly to the photo-conversion device.

22. The imager pixel cell of claim 15, wherein the first reset transistor is arranged to apply the reset voltage directly to the photo-conversion device.

23. The imager pixel cell of claim 15, wherein the first reset transistor is arranged to apply the reset voltage to the photo-conversion device through the second and third transistors.

24. The pixel cell of claim 8, wherein the photo-conversion device is a photodiode.

25. An imager pixel cell comprising:

a semiconductor substrate;

a photo-conversion device supported by the substrate, the photo-conversion device having a charge conversion node;

a first capacitor having one terminal connected to the charge conversion node;

a first transistor formed on the substrate for resetting the charge conversion node to a predetermined voltage;

a second transistor formed on the substrate;

a second capacitor having one terminal connected to the charge conversion node through the second transistor;

a source follower transistor having a gate for receiving the electrical charges; and

a row select transistor for coupling the output of the source follower transistor to an output line.

26. The imager pixel cell of claim 25, wherein the first transistor has a source and drain region, one of the source and drain regions being the charge conversion node.

27. The imager pixel cell of claim 25, wherein the photo-conversion device is a photodiode.

28. The imager pixel cell of claim 25, wherein the second transistor has a source and drain region, one of the source and drain regions of the second transistor is the charge conversion node.

29. The imager pixel cell of claim 25, further comprising:

a third transistor formed on the substrate;

a third capacitor having one terminal connected to the charge conversion node through at least the third transistor.

30. The imager pixel cell of claim 29, wherein the one terminal of the third capacitor is connected to the conversion node through the second and third transistors.

31. The imager pixel cell of claim 29, wherein the third transistor has source and drain regions, one of which is electrically connected to the one terminal of the third capacitor and the other of which is connected by an electrical conductor to the conversion node.

32. The imager pixel cell of claim 29, wherein the third transistor has source and drain regions, one of which is electrically connected to one terminal of the third capacitor and the other of which is connected to the source and drain region of the second transistor which is not the charge conversion node.

33. The imager pixel cell of claim 32, wherein the first transistor has source and drain regions, one of the source and drain regions of the first transistor being the one of the source and drain regions of the third transistor which is electrically connected to the one terminal of the third capacitor.

34. The imager pixel cell of claim 25, wherein the second capacitor stores charge generated by the photo-conversion device, when the charge generated by the photo-conversion device reaches a charge level set by a gate voltage of the second transistor.

35. The imager pixel cell of claim 28, wherein the second capacitor stores charges generated by the photo-conversion device when the charge generated by the photo-conversion device reaches a charge level set by a gate voltage of the second transistor and the third capacitor stores charges generated by the photo conversion device when the charge stored on the second capacitor reaches a charge level set by a gate voltage of the third transistor.

36. The imager pixel cell of claim 29, wherein the second capacitor stores charges generated by the photo-conversion device when the charge generated by the photo-conversion device reaches a charge level set by a gate voltage of the second transistor and the third capacitor stores charges generated by the photo-conversion device when the charges generated by the photo-conversion device reach a charge level set by a gate voltage of the third transistor.

37. The imager pixel cell of claim 25, wherein the first capacitor is formed by parasitic capacitance associated with the charge conversion node.

38. The imager pixel cell of claim 25, wherein the second transistor causes charges to be redistributed among the first and second capacitors during a readout period.

39. The imager pixel cell of claim 29, wherein the second transistor causes charges to be distributed among the first and second capacitors during a first portion of a readout period, and the first and second transistors cause charges to be distributed among the first, second and third capacitors during a second portion of the readout period.

40. The imager pixel cell of claim 25, wherein the gate of the source follower transistor is coupled to the charge conversion node.

41. method for operating an imager, the method comprising:

generating charge from incident light;

storing a first portion of the charge in a first capacitor;

storing a second portion of the charge in a second capacitor when the charge exceeds a limit; and

reading out the first and second portions.

42. method of claim 41, wherein the limit is the storage capacity of the first capacitor.

43. method for operating an imager, the method comprising:

generating charge from incident light;

storing the charge in a sequence of capacitors selectively coupled by a sequence of transistors;

turning on the transistors in sequence such that a later capacitor in the sequence of capacitors stores charge that overflows from an earlier capacitor in the sequence of capacitors; and

reading out charge stored in the sequence of capacitors.

44. A method for increasing the dynamic range of an imager, the method comprising:

converting incident light to an electric charge during an integration period;

storing a first portion of the electric charge in a first storage node;

storing a second portion of the electric charge in a second storage node, wherein the second portion comprises a portion of the electric charge above a first limit;

storing a third portion of the electric charge in a third storage node, wherein the third portion comprises a portion of the electric charge above a second limit;

reading out the first, second, and third portions during a readout period.

45. The method of claim 44, wherein the first limit corresponds to the storage capacity of the first storage node and the second limit corresponds to the storage capacity of the second storage node.

46. The method of claim 45, wherein the first limit is lower than the second limit.

47. A method for operating an imager, the method comprising:

converting incident light into an electric charge;

accumulating a first portion of the electric charge in a first capacitor;

turning on a first transistor coupled between the first capacitor and a second capacitor when the electric charge exceeds the storage capacity of the first capacitor;

accumulating a second portion of the electric charge in the second capacitor; and

reading out charge stored in the first and second capacitors.

48. The method of claim 47, further comprising:

turning on a second transistor coupled between the second capacitor and a third capacitor when the electric charge exceeds the storage capacity of the second capacitor;

accumulating a third portion of the electric charge in the third capacitor; and

reading out charge stored in the third capacitor.

49. The method of claim 47, turning on the first transistor prior to the start of an integration period.