Organic electronic component comprising a patterned, semi-conducting functional layer and a method for producing said component

• US 7,442,954 B2
• Filed: 11/13/2003
• Issued: 10/28/2008
• Est. Priority Date: 11/19/2002
• Status: Expired due to Fees

• Current Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Original Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Inventors: Clemens, Wolfgang, Fix, Walter, Ullmann, Andreas
• Primary Examiner(s): Sarkar; Asok K
• Application Number:
  US10/535,448
• Publication Number:
  US 20060118779A1
• Time in Patent Office: 1,811 Days
• Field of Search: 257/40, 257/E21.051, 438/99, 438/149, 438/164
• US Class Current: 257/40
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/468 characterised by the gate dielectrics
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 71/13 using printing techniques, e.g. ink-jet printing or screen printing

Abstract

The invention relates to an organic electronic component such as an organic field effect transistor and a method for producing said component, the semiconducting layer of the component being patterned, although the component can be produced by an inexpensive printing method. In order to achieve this, the lower functional layer is prepared by a treatment such that it has partial regions on which wetting takes place in the subsequent process step, and partial regions on which wetting is not effected.

Claims

1. An organic electronic component comprising:

a substrate;

a patterned electrically conductive electrode lower layer on and contiguous with a surface of the substrate, the lower layer being formed as a plurality of spaced apart sets of electrodes wherein each set comprises spaced apart source/drain electrodes;

an arrangement on and contiguous with a region of the substrate located between at least two of the sets of said electrodes, the arrangement for precluding the wetting of that substrate region by a subsequently applied organic functional semiconducting layer and to thereby minimize current leakage between the two sets of electrodes; and

a patterned functional organic semiconductor layer on, over and contiguous with the at least two sets of electrodes and on, over, and contiguous with the substrate surrounding the at least two sets of the electrodes to thereby embed the at least two sets of electrodes in the semiconductor layer wherein there is substantially no semiconductor layer overlying or contiguous with the substrate in said region of the substrate.

2. The organic electronic component as claimed in claim 1, further including an electrically insulating layer over the semiconductor layer and the region and a gate electrode over each set of said drain/source electrodes.

5. The electronic organic component according to claim 1 further including an electrically insulating layer over the semiconductor layer and the region and a gate electrode over each set of said drain/source electrodes wherein a set of electrodes, the semiconductor layer and a gate electrode each form an organic field effect transistor (FET) on the substrate to thereby form a plurality of FET transistors, and further including at least one conductor for electrically coupling the plurality of FET transistors into a common circuit and wherein the region exhibits negligible current leakage from and to the FET transistors in the circuit.

3. An organic electronic component comprising:

a substrate;

a lower layer forming a set of spaced apart drain/source electrodes defining a first area of a given peripheral extent on and contiguous with the substrate

a second area of the substrate external the given peripheral extent defining a given substrate region;

an arrangement on the given substrate region for precluding the welling of that given substrate region by a subsequently applied organic functional semiconducting layer;

the arrangement for forming the semiconductor layer into a patterned functional organic semiconductor layer on and contiguous with the substrate in a portion thereof between the second area and the electrodes and overlying and contiguous with the electrodes to thereby embed the electrodes in the semiconductor layer, the second area of the substrate being non-wetted by the semiconductor layer and thereby free of the semiconductor layer;

an electrically insulating layer over and contiguous with at least the semiconductor layer;

an electrically conductive gate electrode over and contiguous with the insulating layer to thereby form a first field effect transistor (FET) with the semiconductor layer and the insulating layer; and

a further FET on and contiguous with the substrate and spaced from the first FET by said region to thereby minimize leakage currents across said region between said first and further FETs.

4. An organic component according to claim 3, including a plurality of said FET transistors on said substrate and electrically conductively interconnected to form a circuit and wherein each said FET is spaced from an adjacent FET by a region which exhibits said minimized leakage currents.

6. A method for producing an organic electronic component comprising:

forming a substrate;

forming a lower layer on and contiguous with the substrate as a set of spaced apart drain/source electrodes defining a first area of a given peripheral extent;

forming a second area of the substrate external the given peripheral extent defining a given substrate region;

forming an arrangement on the given substrate region for precluding the wetting of that given substrate region by a subsequently applied organic functional semiconducting layer;

causing the arrangement to form the semiconductor layer into a patterned functional organic semiconductor layer on and contiguous with the substrate in a portion thereof between the second area and the electrodes and overlying and contiguous with the electrodes to thereby embedded the electrodes in the semiconductor layer, the second area of the substrate being non-wetted by the semiconductor layer and thereby free of the semiconductor layer;

applying an electrically insulating layer over and contiguous with at least the semiconductor layer;

forming an electrically conductive gate electrode over and contiguous with the insulating layer to thereby form a first field effect transistor (FET) with the semiconductor layer and the insulating layer; and

forming a further FET on and contiguous with the substrate and having drain/source electrodes spaced from the drain/source first FET by said region wherein said region thereby minimizes leakage currents there across between said first and further FETs

7. The method of claim 6, wherein the forming the arrangement includes printing a resist layer on the given substrate region.

8. The method of claim 6, wherein the forming the arrangement comprises printing a treatment on the given substrate region.

9. A circuit formed of organic field effect (FET) transistors comprising organic functional layers, the circuit comprising:

a substrate; and

a plurality of adjacent organic FETs on and contiguous with a surface of the substrate, each FET comprising one or more electrically conductive functional layer electrodes forming a drain and a source electrode for each FET on and contiguous with the substrate and a patterned organic semiconducting layer on and contiguous with the one or more of the drain/source electrodes and on and contiguous with a portion of the substrate surface about the drain/source electrodes;

an arrangement on and contiguous with the substrate surface between each of the drain/source electrodes of the next adjacent FETs for precluding the wetting of the substrate by the semiconducting layer to thereby form the pattern of the semiconductor layer on the substrate with the region of the arrangement being free of the semiconductor layer;

the patterned semiconducting functional layer having an electrical interruption between next adjacent components formed by the arrangement precluding the wetting of the substrate by the semiconductor layer, the interruption for minimizing current leakage between the drain/source electrodes of the next adjacent FETs.

10. The circuit of claim 9, wherein the electrical interruption comprises a semiconducting free area on the substrate.

11. The circuit of claim 9, wherein the arrangement includes a resist on the substrate.

12. The circuit of claim 9, wherein the arrangement includes a surface treatment applied to the substrate in the free area for said preventing.